$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

MOS Analog switch driven by complementary, minimally skewed clock signals 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/16
  • H03K-017/687
  • H03K-019/096
출원번호 US-0465408 (1983-02-10)
발명자 / 주소
  • Allgood Robert N. (Austin TX) Peterson Joe W. (Austin TX) Whatley Roger A. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 60  인용 특허 : 7

초록 ▼

An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimi

대표청구항 ▼

An MOS analog switch, comprising: first, second and third MOS transmission gates, each transmission gate having a transistor of first conductivity type utilizing a first current electrode as an input terminal, a second current electrode as an output terminal, and a control electrode, the input termi

이 특허에 인용된 특허 (7)

  1. Lewyn Lanny L. (Palo Alto CA) Lucas Charles H. (Newport Beach CA), Channel charge compensation switch with first order process independence.
    상세보기
  2. White ; William H. ; Lorie ; Mario A., IGFET clock generator.
    상세보기
  3. Culmer Daniel D. (Sunnyvale CA), MOSFET switching device with charge cancellation.
    상세보기
  4. Hatchett John D. (Scottsdale AZ) Olesin Andrew S. (Austin TX), Method for performing a sample and hold function.
    상세보기
  5. Huntington ; Robert Charles, Sample and hold circuit.
    상세보기
  6. Takahashi Masayuki (Utsunomiya JPX) Goto Kunihiko (Kawasaki JPX) Tanaka Hisami (Yokohama JPX) Ohhata Michinobu (Kawasaki JPX), Sample and hold circuit.
    상세보기
  7. Krambeck Robert H. (Warren NJ) Shoji Masakazu (Warren NJ), Skew-free clock circuit for integrated circuit chip.
    상세보기

이 특허를 인용한 특허 (60)

  1. Patrick J. Mullarkey, Apparatus for adjusting delay of a clock signal relative to a data signal.
    상세보기
  2. Schrenk Hartmut (Haar DEX), CMOS-inverter.
    상세보기
  3. Manning Troy A., Circuit and method for specifying performance parameters in integrated circuits.
    상세보기
  4. Theus Ulrich (Gundelfingen DEX) Orben Hans-Josef (Heuweiler DEX), Clocked CMOS circuit with at least one CMOS switch.
    상세보기
  5. Schober Robert C., Coincident complementary clock generator for logic circuits.
    상세보기
  6. Patrick J. Mullarkey, Computer system having memory device with adjustable data clocking.
    상세보기
  7. Mullarkey, Patrick J., Computer system having memory device with adjustable data clocking using pass gates.
    상세보기
  8. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
    상세보기
  9. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
    상세보기
  10. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  11. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  12. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
    상세보기
  13. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  14. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  15. Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
    상세보기
  16. Schuster Stanley E. (Granite Springs NY), ECL to FET interface circuit for field effect transistor arrays.
    상세보기
  17. Shoji Masakazu (Warren NJ), High speed MOS circuits.
    상세보기
  18. Masuda Eiji (Kawasaki JPX), Input signal level detecting circuit.
    상세보기
  19. Keeth Brent ; Baker Russel J., Low skew differential receiver with disable feature.
    상세보기
  20. Keeth Brent, Low-skew differential signal converter.
    상세보기
  21. Keeth Brent, Low-skew differential signal converter.
    상세보기
  22. Keeth, Brent, Memory system with dynamic timing correction.
    상세보기
  23. Mullarkey Patrick J., Method and apparatus for adjusting data timing by delaying clock signal.
    상세보기
  24. Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
    상세보기
  25. Brent Keeth ; Terry R. Lee ; Kevin Ryan ; Troy A. Manning, Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
    상세보기
  26. Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
    상세보기
  27. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  28. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  29. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  30. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  31. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  32. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  33. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
    상세보기
  34. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  35. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  36. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  37. Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.
    상세보기
  38. Troy A. Manning, Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.
    상세보기
  39. Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  40. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  41. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  42. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  43. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  44. Brent Keeth, Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same.
    상세보기
  45. Manning Troy A., Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device.
    상세보기
  46. Troy A. Manning, Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same.
    상세보기
  47. Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
    상세보기
  48. Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
    상세보기
  49. Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.
    상세보기
  50. Briggs Willard S. (Carrollton TX), Non-overlapping clock CMOS circuit with two threshold voltages.
    상세보기
  51. Masleid, Robert Paul, Power efficient multiplexer.
    상세보기
  52. Masleid, Robert Paul, Power efficient multiplexer.
    상세보기
  53. Masleid, Robert Paul, Power efficient multiplexer.
    상세보기
  54. Kim Chang-Hyun (Seoul KRX) Choi Won-Tae (Busan KRX), Semiconductor device having a time delay function.
    상세보기
  55. Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.
    상세보기
  56. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  57. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  58. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  59. Chu Albert M. (Essex Junction VT) Griffin William R. (Shelburne VT), Transistor delay circuits.
    상세보기
  60. Lee Charles M. (New Providence NJ) Murphy Bernard T. (Summit NJ), Trimmable loading elements to control clock skew.
    상세보기

관련 콘텐츠

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로