초록 ▼

Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microprocessor before transferring control of the data a

Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microprocessor before transferring control of the data and address busses to the DMAC and generates one or both of two data transfer strobe signals which instruct the memory to transfer contiguous bytes, contiguous high alternate order bytes, or contiguous low alternate order bytes, or both.

대표청구항 ▼

In a data processing system having a bus system interconnecting the various elements of the data processing system including a plurality of I/0 devices, a memory in which data is stored in words each having a high byte and a low byte, comprising; a processor generating a set of control signals to tr

In a data processing system having a bus system interconnecting the various elements of the data processing system including a plurality of I/0 devices, a memory in which data is stored in words each having a high byte and a low byte, comprising; a processor generating a set of control signals to transfer data indirectly between said I/0 devices and memory on said bus system through said processor in a plurality of different modes, including; a first mode in which data is transferred one word at a time, a second mode in which data is transferred one byte at a time including either high or low contiguous bytes, a third mode in which data is transferred only one high byte at a time, and a fourth mode in which data is transferred only one low byte at a time; a synchronous control means providing transfer signals to transfer data directly between said I/0 devices and memory on said bus system without going through said processor in only a single mode of data transfer; a means for providing plural modes of data transfer during direct memory access using said synchronous control means asynchronously, including; a control signal generation means responsive to said processor and said transfer signals of said control means for generating mode signal substitutes for said set of control signals for transferring data in any of said plural modes, including a decode means for decoding an instruction, sent by the processor to the control signal generation means, into an output signal indicating the type of data transfer; and means coupled to said control signal generation means responsive to said generated mode control signals and the output signal of said decode means for transferring data between said memory and said I/0 devices in accordance with the mode signals generated by the control signal generation means, whereby data can be transferred asynchronously in said plurality of different modes using said synchrounous control means.