초록 ▼

A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets wh

A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.

대표청구항 ▼

1. A dynamic gate array for simulating an overall operation carried out by a combination of logic groups on a primitive signal to provide a derived signal, said logic groups being responsive to input signals for providing output signals, respectively, and being operable in steps in response to said

1. A dynamic gate array for simulating an overall operation carried out by a combination of logic groups on a primitive signal to provide a derived signal, said logic groups being responsive to input signals for providing output signals, respectively, and being operable in steps in response to said primitive signal given as a particular one of said input signals to eventually provide a specific one of said output signals as said derived signal, said dynamic gate array comprising: register means for storing a plurality of logic signals assigned to said steps; decode memory means for memorizing a plurality of decoding patterns assigned to said steps, each decoding pattern defining a set of dependent variables for a set of independent variables, the dependent variable sets being decided by said logic groups for the independent variable sets which said input signals are representative of; gate memory means for memorizing a plurality of logic operations assigned to said steps; and step specifying means for successively specifying said steps for said logic signals, said decoding patterns, and said logic operations to specify, when each step is specified, at least one of said logic signals, at least two of said decoding patterns, and at least one of said logic operations, said at least one logic signal collectively serving as one of said input signals, said step specifying means thereby providing those at least two of said dependent variable sets which are defined by said at least two decoding patterns for those at least two of said dependent variable sets which the last-mentioned one input signal is representative of, subjecting said at least two dependent variable sets to said at least one logic operation to provide one of said output signals, and storing the last-mentioned one output signal in said register means as at least one of said logic signals that is assigned to the step being specified. 2. A dynamic gate array as claimed in claim 1, wherein each input signal consists of eight logic signals. 3. A dynamic gate array as claimed in claim 2, wherein each logic signal is given by a permutation of either of a sequence of logic one states, a sequence of logic zero states, and a sequence of logic one and zero states, said permutation having elements equal in number to sixteen.