초록 ▼

A FSK demodulation circuit using counter techniques to distinguish between two transmitted frequencies, provides a delay preceding the change points of the demodulated signal to reduce signal distortion. Presettable counters reduce the number of data bits for processing, and a plurality of counters

A FSK demodulation circuit using counter techniques to distinguish between two transmitted frequencies, provides a delay preceding the change points of the demodulated signal to reduce signal distortion. Presettable counters reduce the number of data bits for processing, and a plurality of counters count an equal plurality of zero-cross intervals to reduce distortion. Registers and multiplexer further reduce circuit complexity.

대표청구항 ▼

1. A circuit for demodulating an FSK signal that has first and second frequencies which respectively correspond to the high and the low of a binary signal, the circuit comprising: clock means having a train of clock pulses as an output; detector means responsive to an FSK input signal to provide

1. A circuit for demodulating an FSK signal that has first and second frequencies which respectively correspond to the high and the low of a binary signal, the circuit comprising: clock means having a train of clock pulses as an output; detector means responsive to an FSK input signal to provide a zero-cross output signal having zero-cross intervals; N counter means, where N is equal to or greater than 2, each counter means having the clock pulses as an input and responding in succession to count the clock pulses in N zero-cross intervals of the zero-cross signal to provide an output; means for dividing the output of each counter means in sequence by N to provide an average count value for each zero-cross interval, the possible error in the count value for each interval so produced being decreased by 1/N; means for comparing each successive average count value with a predetermined threshold count value to provide a comparison signal output; and storage means having a demodulated binary signal as an output in which transitions in the output are delayed by the comparison signal. 2. A circuit for demodulating an FSK signal in accordance with claim 1, in which the counter means, the dividing means, and the storage means are each responsive to a respective control signal; the demodulating circuit further comprising: control means having the clock signal and the zero-cross signals as input and having a plurality of control signals as outputs. 3. A circuit for demodulating an FSK signal in accordance with claim 1, in which the predetermined threshold count value is experimentally determined by measuring at least one of the influence the transmission line and the band pass filter upon a received signal. 4. A circuit for demodulating an FSK signal in accordance with claim 1 in which each of the N counters is pre-settable and further comprising: memory means for supplying the 2's complement of the predetermined threshold count value to each of the N counters when counting is initiated. 5. A circuit for demodulating an FSK signal in accordance with any one of claim 1 and claim 4 in which the predetermined threshold count value is the most suitable threshold interval obtained while slightly varying the threshold interval. 6. A circuit for demodulating an FSK signal in accordance with claim 1 in which the predetermined threshold count value is the most suitable value obtained by receiving a test wave form before an FSK signal. 7. A circuit for demodulating an FSK signal in accordance with claim 1 in which the N counter means further comprises: single counter means for successively counting each zero-cross interval to provide a count value therefor; N register means, each storing, in succession, a count value output of the single counter means; and adder means having the N count values stored in the register means as an input and having the sum of the N count values as an output. 8. A circuit for demodulating an FSK signal in accordance with claim 7 in which the single counter means is pre-settable and further comprising: memory means for supplying the 2's compliment of the predetermined threshold count value to each of the N registers at the time of starting to count. 9. A circuit for demodulating an FSK signal in accordance with claim 1 and further comprising: means for storing the predetermined threshold count value; decision means responsive to an input test wave form received prior to the FSK signal for deciding the most suitable value of the threshold count value. 10. A circuit for demodulating an FSK signal in accordance with claim 9 in which each of the N counters is a presettable counter and further comprising: means for setting a threshold count value stored in the memory means as 2's compliments to each of the N counters prior to counting the N zero-cross intervals. 11. A circuit for demodulating an FSK signal in accordance with claim 9 in which the N counters comprise; single counter means for counting each successive zero-cross interval to provide an output; N register means each having a count value for a succeeding zero-cross interval as an input; and in which the adder means have the N count values stored in succession in each register means as inputs.