초록 ▼

Superconductive integrated logic gate circuits of the magnetically controlled type incorporating Josephson tunnel junctions utilize a superconductive layer that forms a base electrode for Josephson junction devices on the integrated circuit, a ground plane, and magnetic control lines. A layer of sup

Superconductive integrated logic gate circuits of the magnetically controlled type incorporating Josephson tunnel junctions utilize a superconductive layer that forms a base electrode for Josephson junction devices on the integrated circuit, a ground plane, and magnetic control lines. A layer of super-conductive material superposed on a barrier layer provides inductive loops connected to junction counterelectrodes and coupled to the magnetic control lines. By patterning the control lines in the same plane as the ground plane-base electrode layer, two layers, an insulating layer and a super-conductive layer, can be eliminated from the prior art structure of a 1:2:1 magnetically controlled logic gate interferometer. A preferred embodiment utilizing an all refractory superconductor-barrier-superconductor trilayer patterned by local anodization is also described. Processes for manufacturing the embodiments of the invention are disclosed.

대표청구항 ▼

1. A superconductive logic device comprising: (a) a first layer of superconductive material, including at least one inductive loop of superconductive material for magnetic control and a ground plane, said loop and said ground plane coplanar with said first layer, (b) a barrier layer overlaying s

1. A superconductive logic device comprising: (a) a first layer of superconductive material, including at least one inductive loop of superconductive material for magnetic control and a ground plane, said loop and said ground plane coplanar with said first layer, (b) a barrier layer overlaying said first layer, (c) a second layer of superconductive material, superposed on said barrier layer such that at least two superconductive junctions are formed by said first and second superconductive layers and said barrier layer, whereby tunneling currents can flow therethrough between said supercondutive layers, and (d) a third layer of superconductive material including at least one inductive loop of superconductive material superposed with respect to said first and second superconductive layers with insulating means therebetween, conductively coupled to said two superconductive junctions, and responsive to inductive coupling from said inductive loop for magnetic control for biasing said superconductive junctions thereby interrupting at least a portion of said tunneling currents when a predetermined current is applied to said inductive loop for magnetic control. 2. The logic device of claim 1, further comprising a plurality of said superconductive junctions having base electrodes in said first layer with a common electrical connection, and including a plurality of counter electrodes in said second layer, ones of said counter electrodes respectively superposed over ones of said base electrodes. 3. The logic device of claim 1, including a large area contact junction having a lower electrode in said first layer of superconductive material, an upper electrode in said second layer of superconductive material, and a large area tunneling barrier therebetween, said area of said large contact junction being such that said large area contact junction has a critical current so as to remain at zero junction voltage at all current loadings of said junction, so that electrical contact of substantially zero resistance is effected from said second layer of superconductive material to said first layer of superconductive material by means of said large area contact junction. 4. The logic device of claim 1 in which said first and second layers of superconductive material are patterned to form at least one flux trapping site therein, said site comprised of a region wherein said superconductive material has been removed in proximity to said inductive loops for magnetic control and junction biasing. 5. The logic device of claim 4, further comprising a region of superconductive material superposed over said first and second layers of superconductive material and adjoining said flux trapping site, thereby constituting an area of multiple thickness of superconductive material substantially thicker than said first and second layers. 6. The logic device of claim 1, wherein said inductive loop for magnetic control further comprises first waveguide transmission line means coplanar with said ground plane, for magnetically biasing said at least two superconductive junctions. 7. The logic device of claim 3, said third layer of superconductive material further comprising second waveguide transmission line means substantially coplanar with said ground plane and conductively coupled to said upper electrodes of said large area contact junction, said second waveguide transmission line means being further magnetically coupled to said at least one inductive loop for magnetic control, for magnetically biasing said at least two superconductive junctions. 8. The logic device of claim 7 wherein said insulating means defines an opening therethrough superposed over said ground plane and said second transmission line means is superposed over said opening thereby defining a capacitor, with said insulating means constituting a dielectric for said capacitor. 9. The logic device of claim 1, wherein said second layer of superconductive material is anodized through to said barrier layer except at the location of said superconductive junctions. 10. The logic device of claim 9, wherein said barrier layer is further free from anodization at the locations of said large area contact junctions, said first and second layers of superconductive material with said barrier layer therebetween and with said second superconductive layer anodized therethrough comprising a Trilayer. 11. The logic device of claim 10, including a layer of resistive material deposited over said anodized second layer of superconductive material and beneath said insulating means, said layer of resistive material being patterned to form resistors for said logic device. 12. A superconductive logic device comprising: (a) a first layer of superconductive material, including at least one inductive loop of superconductive material for magnetic control and a ground plane, said loop and said ground plane coplanar with said first layer, (b) a layer of insulating material overlaying said first layer, having openings therethrough defining a plurality of superconductive junctions, (c) a barrier layer overlaying said openings (d) a second layer of superconductive material, superposed on said barrier layer, such that at least two superconductive junctins are formed by said first and second superconductive layers and said barrier layer, whereby tunneling currents can flow therethrough between said superconductive layers, said second layer of superconductive material defining at least one inductive loop superposed with respect to said first superconductive layer, and responsive to inductive coupling from said loop for magnetic control for biasing said at least two superconductive junctions, thereby interrupting said tunneling currents when a predetermined current is applied to said inductive loop for magnetic control. 13. The logic device of claim 12, said plurality of superconductive junctions having base electrodes in said first layer with a common electrical connection, and including a plurality of counter electrodes in said second layer respectively superimposed over said base electrodes. 14. The logic device of claim 12, including a large area contact junction having a lower electrode in said first layer of superconductive material, an upper electrode in said second layer of superconductive material, and a large area tunneling barrier therebetween, said area of said large area contact junction being such that said large area contact junction has a critical current so as to remain at zero junction voltage at all current loadings of said junction, so that electrical contact of substantially zero resistance is effected from said second layer of superconductive material to said first layer of superconductive material by means of said large area contact junction. 15. The logic device of claim 12, in which said first and second layers of superconductive material are patterned to form at least one flux trapping site therein, said site comprised of a region wherein said superconductive material has been removed in proximity to said inductive loops for magnetic control and junction biasing. 16. The logic device of claim 15, further comprising a region of superconductive material superposed over said first and second layers of superconductive material and adjoining said flux trapping site, thereby constituting an area of multiple thicknesses of superconductive material substantially thicker than said first and second layers. 17. The logic device of claim 12, wherein said inductive loop for magnetic control further comprises first waveguide transmission line means coplanar with said ground plane, for magnetically biasing said at least two superconductive junctions. 18. The logic device of claim 14, said second layer of superconductive material further comprising second waveguide transmission line means substantially coplanar with said ground plane and electrically coupled to said upper electrodes of said large area contact junction, said second waveguide transmission line means being further magnetically coupled to said at least one inductive loop for magnetic control, for magnetically biasing said at least two superconductive junctions. 19. The logic device of claim 18, wherein said layer of insulating material defines an opening therethrough superposed over said ground plane and said second transmission line means is superposed over said opening thereby defining a capacitor, with said insulating material constituting a dielectric for said capacitor. 20. The logic device of claim 12, including a layer of resistive material deposited over said insulating layer and beneath said barrier layer, said layer of resistive material being patterned to form resistors for said logic device.