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An apparatus for use with an amplifier regulates the current through a load according to a drive signal having first and second states and comprises switchless sensing means and polarity correction means. The switchless sensing means provides a sense signal continuously representative of the magnitu

An apparatus for use with an amplifier regulates the current through a load according to a drive signal having first and second states and comprises switchless sensing means and polarity correction means. The switchless sensing means provides a sense signal continuously representative of the magnitude of the current through the load without the use of switching circuitry. The polarity correction means is directly coupled to the sensing means and receives the sense signal and is responsive to the status of the drive signal for providing an analog signal continuously representative of both the instantaneous magnitude and polarity of the current through the load.

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1. Apparatus for use with an amplifier regulating the current through a load according to a drive signal having first and second states comprising: (a) a single switchless sensing means disposed in a current path through which load current flows regardless of the polarity of the load current for

1. Apparatus for use with an amplifier regulating the current through a load according to a drive signal having first and second states comprising: (a) a single switchless sensing means disposed in a current path through which load current flows regardless of the polarity of the load current for providing a sense signal continuously representative of the magnitude of the current through the load without the use of switching circuitry; (b) polarity correction means directly coupled to the sensing means, receiving the sense signal and responsive to the status of the drive signal for providing an analog signal continuously representative of both the instantaneous magnitude and polarity of the current through the load. 2. Apparatus according to claim 1 wherein the polarity correction means further comprises means for supplying the sense signal in an inverted form when the drive signal is in the first state, for supplying the sense signal in a non-inverted form when the drive signal is in the second state and for providing a composite of the inverted and non-inverted forms of the sense signal, the composite being the analog signal. 3. Apparatus according to claim 1 wherein the amplifier is a full wave commutation bridge circuit having output terminals and first and second power input terminals, the first power input terminal being connected to one side of a power supply, the load being connected across the output terminals of the bridge circuit, the sensing means comprising a sense resistor connecting the second power input terminal to the return path of the power supply so that the current through the load flows through the sense resistor, the voltate across the sense resistor being the sense signal. 4. Apparatus according to claim 3 wherein the drive signal is a pulse width modulation (PWM) signal applied to drive signal input terminals of the full wave commutation bridge circuit for regulating the current through the load in accordance with the duty cycle of the PWM signal, the polarity correction means comprising switch means and differential input amplifier means, the switch means receiving the sense signal and being responsive to the PWM signal to supply the sense signal to the inverting input of the differential input amplifier means when the PWM signal is in the first state and to supply the sense signal to the non-inverting input of the differential input amplifier means when the PWM signal is in the second state, the output of the differential input amplifier means thereby supplying the sense signal in an inverted form when the PWM signal is in the first state and in a non-inverted form when the PWM signal is in the second state, the output of the differential input amplifier means being the analog signal. 5. Apparatus according to claim 3 wherein the drive signal is a pulse width modulation (PWM) signal applied to drive signal input terminals of the full wave commutation bridge circuit for regulating the current through the load in accordance with the duty cycle of the PWM signal, the polarity correction means comprising first and second switch means and first and second differential input amplifier means, the sense signal being supplied to the inverting input of the first differential input amplifier means and to the non-inverting input of the second differential input amplifier means, the first differential input amplifier means being effective to supply the sense signal in an inverted form at the output thereof, the second differential input amplifier means being effective to supply the sense signal in a non-inverted form at the output thereof, the first switch means being operatively connected to the output of the first differential input amplifier means and being responsive to pass the output thereof when the PWM signal is in the first state and not to pass the output thereof when the PWM signal is in the second state, the second switch means being operatively connected to the output of the second differential input amplifier means and being responsive to pass the output thereof when the PWM signal is in the second state and not to pass the output thereof when the PWM signal is in the first state, the first and second switch means thereby providing the analog signal. 6. Apparatus according to claim 4 or 5 wherein the load is a brushless DC motor. 7. Apparatus comprising: (a) an amplifier driven by a pulse width modulation (PWM) signal for regulating the current supplied to a load; (b) a single switchless sensing means disposed in a current path through which load current flows regardless of the polarity of the load current for providing a sense signal continuously representative of the magnitude of the current through the load without the use of switching circuitry; (c) switching signal means for providing first and second switching signals derived from the PWM signal; (d) polarity correction means directly coupled to the sensing means and receiving the sense signal and responsive to the first switching signal for supplying the sense signal in an inverted form during at least a portion of the time that the PWM signal is in a first state and to the second switching signal for supplying the sense signal in a non-inverted form during at least a portion of the time that the PWM signal is in a second state, the polarity correction means providing an analog signal continuously representative of both the instantaneous polarity and magnitude of the current through the load. 8. Apparatus according to claim 7 wherein the first switching signal is in an active state during at least a portion of the time the PWM signal is in the first state and is in an inactive state at all other times and the second switching signal is in an active state during at least a portion of the time the PWM signal is in the second state and in an inactive state at all other times and the switching signal means further comprises time delay means for interposing a time delay between the occurrence of the active states of the first and second switching signals. 9. Apparatus according to claim 8 wherein the amplifier is a full wave commutation bridge circuit having output terminals and first and second power input terminals for connection to a power supply, the first power input terminal being connected to the positive side of the power supply, the load being connected across the output terminals of the bridge circuit, the sensing means comprising a sense resistor connecting the second power input terminal of the bridge circuit to the return path of the power supply so that the current through the load flows through the sense resistor, the voltage across the sense resistor being the sense signal. 10. Apparatus according to claim 9 wherein the switching signal means comprises a plural stage shift register operatively connected to a logic circuit, the shift register having a clock input driven by a source of clock pulses, the PWM signal being supplied to the input of the first stage of the shift register, the logic circuit receiving the outputs of the last stage and a selected intermediate stage of the shift register and supplying the switching signals, the time delay between the occurrence of the first and second switching signals substantially corresponding to the clock period multiplied by the number of shift register stages between the last stage and the selected intermediate stage. 11. Apparatus according to claim 10 wherein the polarity correction means comprises first and second differential input amplifiers and first and second switch means, the sense signal being applied to the inverting input of the first differential input amplifier and to the non-inverting input of the second differential input amplifier, the output of the first differential input amplifier being applied to the first switch means and the output of the second differential input amplifier being applied to the second switch means, the first switch means being responsive to the first switching signal to pass the output of the first differential input amplifier only when the first switching signal is in the active state, the second switch means being responsive to the second switching signal to pass the output of the second differential amplifier only when the second switching signal is in the active state. 12. Apparatus according to claim 10 wherein the polarity correction means comprises a differential input amplifier and first and second switch means, the first and second switch means receiving the sense signal, the first switch means being responsive to the first switching signal to apply the sense signal to the inverting input of the differential input amplifier when the first switching signal is in the active state, the differential input amplifier thereby supplying the sense signal in an inverted form when the first switching signal is in the active state, the second switch means being responsive to the second switching signal to apply the sense signal to the non-inverting input of the differential input amplifier when the second switching signal is in the active state, the differential input amplifier thereby supplying the sense signal in a non-inverted form when the second switching signal is in the active state. 13. Apparatus according to claim 11 wherein the polarity correction means further comprises buffer amplifier means for receiving the signal from the first and second switch means and holding during the time delay the last value of the signal supplied by the first and second switch means before the time delay occurred. 14. Apparatus according to claim 12 wherein the polarity correction means means further comprises third switch means operatively connected to the output of the differential input amplifier for passing the output signal of the differential input amplifier only when either of the first or second switching signals is in the active state. 15. Apparatus according to claim 14 wherein the polarity correction means further comprises buffer amplifier means for receiving the signal from the third switch means and holding during the time delay the last value of the signal supplied by the third switch means before the time delay occurred. 16. Apparatus according to claim 13 or 15 wherein the load is a brushless DC motor. 17. Apparatus for providing a current feedback signal continuously representative of instantaneous polarity and magnitude of the load current through a brushless DC motor regulated by a full wave commutation bridge which is driven by a pulse width modulation (PWM) signal and which receives a source of current from a power supply, comprising: (a) a sense resistor connecting the bridge circuit to the return path of the power supply so that the current through the load flows through the sense resistor, the voltage across the sense resistor defining a sense signal; (b) a plural stage shift register which is clocked by a source of clock pulses, the input of the first stage of the shift register receiving the PWM signal, the outputs of the last stage and a selected intermediate stage of the shift register being supplied to a logic circuit, the logic circuit providing first and second switching signals, the switching signals each having an active state and an inactive state, the first switching signal being active during at least a portion of the time that the PWM signal is in a first state and being inactive at all other times, the second switching signal being active during at least a portion of the time that the PWM signal is in a second state and being inactive at all other times, the shift register providing a time delay between subsequent occurrences of the active state of the first and second switching signals, the duration of the time delay substantially corresponding to the clock period multiplied by the number of stages between the last stage and the selected intermediate state of the shift register; (c) differential input amplifier and switch means responsive to the first and second switching signals for providing the sense signal in an inverted form when the first signal is in the active state and for providing the sense signal in a non-inverted form when the second signal is in the active state; (d) signal holding means receiving the signal provided by the differential input amplifier and switch means for holding during the time delay the last value of the signal supplied by the differential input and switch means before the time delay occurred. 18. A method of providing an analog signal continuously representative of both the instantaneous polarity and magnitude of the current through a load driven by a pulse width modulation (PWM) signal, the method comprising: (a) sensing the current through the load by means of a signle sensing element disposed in a current path through which load current flows regardless of the polarity of the load current and switchlessly providing a sense signal representative of the magnitude of the current through the load; (b) inverting the polarity of the sense signal during at least a portion of the time that the PWM signal is in a first state; (c) passing the sense signal in a non-inverted form during at least a portion of the time that the PWM signal is in a second state; (d) combining the signals obtained in steps (b) and (c) to obtain the analog signal. 19. Apparatus according to claim 1 wherein the load is a multi-phase load. 20. Apparatus according to claim 1 wherein the load current is a direct current. 21. Apparatus according to claim 7 wherein the load is a multi-phase load. 22. Apparatus according to claim 7 wherein the load current is a direct current.