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Control system primarily responsive to signals from digital computers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05B-015/08
  • G05B-009/02
  • G06F-007/02
  • H04L-001/00
출원번호 US-0498860 (1983-05-27)
우선권정보 GB-0016234 (1982-06-03)
발명자 / 주소
  • Burrage Robert G. (Solihull GB2) Glaze Stanley G. (Kingswinford GB2) Tipton James (Solihull GB2)
출원인 / 주소
  • Lucas Industries (GB2 03)
인용정보 피인용 횟수 : 24  인용 특허 : 10

초록

A system controlled by digital computers includes first and second dissimilar digital computers which are distinctly programmed to generate respective nominally identical control signals alternately. The computer alternately generates limiting values for the control signals, each limiting value bein

대표청구항

A control system which is primarily controlled by a digital computer, said system comprising: (a) an apparatus responsive to input control signals, (b) and a computer arrangement comprising: (1) first and second digital computers which have different hardware designs and which are programmed with re

이 특허에 인용된 특허 (10)

  1. Frye Robert C. (Rte. 2 ; Box 255 Winchester KY 40391), Automatic process control device.
  2. Meredith ; James F. ; Williams ; Brian, Control systems.
  3. Doniger Jerry (Montvale NJ) Kirchhein Albert T. (Montvale NJ) Reynolds Gibson (Tuxedo NY), Controller for a dual servo system.
  4. Burrage Robert G. (Solihull GB2), Digital control system including means for maintaining signals supplied thereby within limiting values.
  5. Strelow ; Horst, Digital data computer processing system.
  6. McDonald John C. (Los Gatos CA) Baichtal James R. (Los Altos CA), Double redundant processor.
  7. Eki Yurio (Hitachi JPX) Tennichi Yasuhiro (Hitachi JPX) Honda Naganobu (Hitachi JPX), Electro-hydraulic governor employing duplex digital controller system.
  8. Piras Giancarlo (Milan ITX), Parallel multiprocessing system for an industrial plant.
  9. Azegami Tadashi (Inagi JPX), Process control system.
  10. Dobler Karl-Ulrich (Waiblingen DEX) Mura Sigurd (Leonberg DEX) Kraft Erhard (Hemmingen DEX), System for controlling track-bound vehicles forming a train.

이 특허를 인용한 특허 (24)

  1. Chong Ray K. ; Gunn Peter D. ; Herald Richard A., Apparatus for synchronizing flight management computers where only the computer chosen to be the master received pilot.
  2. Murphy Richard D. (Trumbull CT) Fischer William C. (Monroe CT), Backup control system (BUCS).
  3. Ishizawa Yasuhisa,JPX, Data communication control apparatus and method for controlling date communication among at least one data processing ap.
  4. Hurst David C. (Knowle GB2) Brearley Malcolm (Solihull GB2), Dual computer cross-checking system.
  5. Johansson, Rikard; Wistedt, Kjell, Fault tolerant control system.
  6. Perks Malcolm (Hertfordshire GB2), Helicopter rotor and engine control.
  7. Chandran Strikumar R. (San Jose CA) Rhodes Edward J. (Los Gatos CA) Lui Albert S. (San Jose CA) Walker Mark S. (San Jose CA), High level self-checking intelligent I/O controller.
  8. Macias-Garza Fernando,MXX ; Miller Todd W. ; McGraw Montgomery C., Method and apparatus for comparing real time operation of object code compatible processors.
  9. Klaiber Alex ; Bedichek Robert ; Keppel David, Method and apparatus for correcting errors in computer systems.
  10. Sandham, John H.; Knowles, Paul T., Method and apparatus for performing incremental validation of program code conversion.
  11. Fennel, Helmut; Latarnik, Michael, Method for detecting errors of microprocessors in control devices of an automobile.
  12. Gruere Yves M,FRX ; DeMichel Laurent A,FRX ; Le Gall Herve L,FRX, Microprocessor based reliability system applicable, in particular, to the field of rail transport.
  13. Kametani Masatsugu,JPX, Processor element having a plurality of CPUs for use in a multiple processor system.
  14. Kametani Masatsugu (Ibaraki-ken JPX), Processor element having a plurality of processors which communicate with each other and selectively use a common bus.
  15. Fleischmann, Marc; Anvin, H. Peter, Restoring processor context in response to processor power-up.
  16. Hiroyuki Ohta JP; Hideo Miura JP; Mitsuo Usami JP; Masatsugu Kametani JP; Munetoshi Zen JP; Noriaki Okamoto JP, Semiconductor device and method for fabricating the same.
  17. Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
  18. Fleischmann, Marc; Anvin, H. Peter, System and method for saving and restoring a processor state without executing any instructions from a first instruction set.
  19. Moriyama Junichi (Kawasaki JPX) Iwasaki Masaaki (Kawasaki JPX), System for determining and storing valid status information received from cross coupled unit.
  20. Kelly, Edmund; Cmelik, Robert; Wing, Malcolm, Translated memory protection.
  21. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  22. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  23. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  24. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
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