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An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in the array having logic means and a memory for storing a memory state. The first row of the cells in

An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in the array having logic means and a memory for storing a memory state. The first row of the cells in the array forms a parallel input to the array. The last row of said cells in the array forms a parallel output from the array. The cells in the intermediate cells rows between the first and last rows are coupled to at least one cell in a previous cell row. The logic means in each cell computes a new data value based upon the input or inputs from such previous row cells and its present memory state. Each cell is further coupled to at least one cell in the subsequent row of cells. The computed new data value is provided as an output to the coupled cell or cells in the subsequent cell row. Each of the intermediate row cells are coupled to immediately adjacent neighbor cells of the same row to supply the new data value to these neighbor cells and correspondingly receive computed new data values from these same cells. The logic means in each cell compares the new data values received from such neighbor cells with its computed new value and accordingly updates its memory state based upon the results of the comparison.

대표청구항 ▼

An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in said array having logic means and a memory for storing a memory state, the first row of said cells

An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in said array having logic means and a memory for storing a memory state, the first row of said cells in the array forming a parallel input to the array, the last row of said cells in the array forming a parallel output from the array, the cells in the intermediate cell rows between said first and last rows coupled to at least one cell in a previous cell row, said logic means in each cell to compute a new data value based upon said input and its present memory state, said each cell coupled to at least one cell in a subsequent cell row, said new data value provided as an output to said subsequent cell row, each of said intermediate row cells coupled to immediately adjacent neighbor cells of the same row to supply said new data value to said neighbor cells and correspondingly receive new data values from said neighbor cells, said logic means in each cell to compare the new data values received from said neighbor cells with its computed new data value and accordingly update its memory state based upon the results of said comparison.