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A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital m

A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of the synchronizing signal by a predetermined number of bits. The synchronizing signal detecting circuit comprises a counter which is reset when a synchronizing signal detection output which has been discriminated as being correct by use of the error checking code is continuously obtained for N times, where N is a natural number greater than or equal to two.

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A synchronizing signal detecting circuit in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, each of said blocks being made up of digital data which are information signals subjected to a digital modulation,

A synchronizing signal detecting circuit in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, each of said blocks being made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of said synchronizing signal by a predetermined number of bits, said synchronizing signal detecting circuit comprising: a first detecting circuit supplied with said digital signal, for detecting a signal having the same fixed pattern as said synchronizing signal within the digital signal; an error checking circuit for essentially detecting whether said synchronizing signal is correct by use of the error checking code within the digital signal at a point which is a transmitting duration of said predetermined number of bits after a point when a detection signal was produced from said first detecting circuit; extracting means for extracting a clock signal from said digital signal; a first counter for counting pulses in the clock signal which is extracted in said extracting means; first decoder means for producing from a counted output of said first counter a signal having a period which is substantially equal to a period of a signal of one block; counting means reset responsive to an output signal of said error checking circuit when said error checking circuit detects that said synchronizing signal is correct, for counting pulses in a signal which is obtained from an output signal of said first counter and has a period which is substantially equal to the period of the signal of one block; delay means supplied with a counted output of said counting means, for producing a pulse signal which has been delayed by a predetermined delay time from a point when the counted output of said counting means becomes equal to M, where M is a natural number greater than or equal to 2; resetting means for resetting said first counter responsive to the output detection signal of said first detecting circuit immediately after said delay means produces an output pulse signal or immediately after said first decoder produces an output signal; a second detecting circuit for detecting that the output signals of said first detecting circuit and said first decoder means continuously coincide for N times for every period of the signal of one block in a state where the value of the counted output of said counting means is zero, where N is a natural number greater than or equal to 2; a second counter reset responsive to the output detection signal of said first detecting circuit in a duration in which a detection signal is produced from said second detecting circuit, for counting pulses in said clock signal; and second decoder means for decoding a counted output of said second counter, and for producing a synchronizing signal detection signal.