초록 ▼

An electronic control (10) for generating control, diagnostic, and fault signals for a diesel engine (12) with a turbocharger (22) and an injection pump (14). The control (10) provides an injection pump control (78), a turbocharger control (80), a fault monitor (82) and a sequencing control (84). Th

An electronic control (10) for generating control, diagnostic, and fault signals for a diesel engine (12) with a turbocharger (22) and an injection pump (14). The control (10) provides an injection pump control (78), a turbocharger control (80), a fault monitor (82) and a sequencing control (84). These controllers are embodied as a stored program of a microprocessor controlled processor, timing, and memory module (228). The module (228) communicates with an input section receiving analog and discrete inputs via a serial input data line (CRUIN) and further communicates with an output section generating analog and discrete outputs via a serial output data line (CRUOUT).

대표청구항 ▼

A digital control system having a processor for executing a program sequence stored in a memory, said processor and memory communicating with each other through a data bus, an address bus, and a control bus, said processor further provided with a serial input data line, a serial output data line, an

A digital control system having a processor for executing a program sequence stored in a memory, said processor and memory communicating with each other through a data bus, an address bus, and a control bus, said processor further provided with a serial input data line, a serial output data line, and a serial data clock line, said system further comprising: an input section including an analog input multiplexer and a discrete input multiplexer, said analog input multiplexer having a plurality of analog input channels individually connectable to a single analog output and means, responsive to a channel address, for selecting the analog input channel connected to the output; an analog to digital converter having a plurality of digital data outputs for representing a converted analog parameter, an analog input for receiving said analog parameter connected to the output of said analog input multiplexer, a conversion request line for initiating an analog to digital conversion, and an additional digital output line for indicating when a conversion has been completed; a parallel to serial converter responsive to a selection signal, having a plurality of digital inputs connected to the digital outputs of said analog to digital converter and operable to shift the bits on its inputs onto a serial output line which is connected to said serial data input line of said processor; an input multiplexer control for generating said channel address for said analog input multiplexer, said conversion request for said analog to digital converter, said selection signal for said parallel to serial converter, and a selection signal for said discrete input multiplexer from information on said address bus and said serial data clock line; an output section including a serial to parallel converter having a data input connected to said output data line of the processor and a plurality of digital outputs individually connectable to said data input, and further having means, responsive to an output channel address, for selecting the digital output connected to said input; an output multiplexer control for generating said output channel addresses from information on said address bus and said serial data clock line.