초록 ▼

In the non-volatile semiconductor memory of present invention, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the f

In the non-volatile semiconductor memory of present invention, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the floating gate at the surface portion under the edge of the floating gate covered by the select gate.

대표청구항 ▼

A non-volatile semiconductor memory device comprising: a semiconductor substrate; a source region and drain region disposed in spaced apart isolation from one another adjacent to the surface of said semiconductor substrate; a first gate insulating layer on said drain region; a channel extending betw

A non-volatile semiconductor memory device comprising: a semiconductor substrate; a source region and drain region disposed in spaced apart isolation from one another adjacent to the surface of said semiconductor substrate; a first gate insulating layer on said drain region; a channel extending between said source region and said drain region, the channel consisting of a first channel region and a second channel region in contact with one another, the second channel region being in contact with the drain region; a second gate insulating layer on said first channel region; a third gate insulating layer on the second channel region; a floating gate electrode on said first and third gate insulating layers; a select gate electrode on said second gate insulating layer; and means operable in a write mode for applying a drain write voltage VDW of one polarity to said drain region and for applying a select gate write voltage VSGW of said one polarity to said select gate electrode in order to write in the memory and operable in a read mode for applying a drain read voltage VDR of said one polarity to said drain region and for applying a select gate read voltage VSGR of said one polarity to said select gate electrode in order to read out the memory by detecting the drain current dependent on electric charges memorized in the floating gate electrode so as to satisfy the following relations: VSGR≥VSGW, and fS>fC where fS represents the surface potential of said semiconductor substrate, and fC represents the barrier energy potential between said semiconductor substrate and said third gate insulating layer in order to accelerate electrons escaping from said source region and inject some of the accelerated escaping electrons into said floating gate electrode at a position where said first and second channel regions make contact with one another, said position being located sufficiently far from the drain region so as to greatly increase the number of accelerated escaping electrons injected into said floating gate.