초록 ▼

An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric la

An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer. A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer. Then, the upper portion of the insulating layer is deposited over the lower portion, the metallization pattern opened, and the pattern filled with metal up to and even with the top surface of the upper portion of the insulating layer. The metal filling step is produced by depositing a metal layer over the corresponding portion of opened insulating layer, masking the opened regions and selectively and directionally removing the unprotected metal layer.

대표청구항 ▼

A method of forming a planar conductor-insulator layer on a surface of an integrated circuit chip comprising the steps of: (a) forming an insulating layer on the surface of the integrated circuit chip, (b) forming a recess in the insulating layer, (c) depositing a layer of conductive material on th

A method of forming a planar conductor-insulator layer on a surface of an integrated circuit chip comprising the steps of: (a) forming an insulating layer on the surface of the integrated circuit chip, (b) forming a recess in the insulating layer, (c) depositing a layer of conductive material on the insulating layer to a thickness sufficient to fill the recess, thereby leaving a recess in the conductive layer, (d) forming a mask by: (1) depositing a layer of masking material on top of the conductive layer such that the thickness of the layer of masking material in the region overlying the recess in the conductive layer is greater than in other regions of the masking layer, and (2) etching the layer of masking material to expose the top surface of the conductive layer in the regions outside the region overlying the recess in the conductive layer, such that masking material remains in the region overlying the recess in the conductive layer, (e) etching the exposed surface of the conductive layer to remove the portion of the conductive layer in regions outside the region of the recess in the insulating layer, thereby to leave the recess in the insulating layer filled with conductive material.