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Method of fabricating a chip interposer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-004/00
출원번호 US-0639988 (1984-08-13)
발명자 / 주소
  • Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 52  인용 특허 : 9

초록 ▼

Disclosed is a method of fabricating a multichip interposer comprising an insulating support with thin film fine line metallization on one side thereof. A layer of masking material is adhered to in other side and selective areas of the masking material are removed in a desired pattern to expose area

대표청구항 ▼

A method of fabricating an interposer for connecting a plurality of semiconductor chips to a substrate, comprising, in sequence, the steps of: providing an insulating support having a thin film fine line metallization formed on its top surface before the top surface is interrupted by holes interferi

이 특허에 인용된 특허 (9)

  1. Bajorek Christopher H. (Goldens Bridge NY) Chance Dudley A. (Danbury CT) Ho Chung W. (Chappaqua NY), Capacitive chip carrier and multilayer ceramic capacitors.
    상세보기
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  3. Dougherty William E. (Wappingers Falls NY) Greer Stuart E. (Poughkeepsie NY), Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations di.
    상세보기
  4. Wolf Stanley (Sunset Beach CA) Atwood Warren C. (Los Angeles CA), Polyimide inter-metal dielectric process.
    상세보기
  5. Johnson Daniel D. (Yorklyn DE) Fritz Herbert L. (Englishtown NJ), Process for forming conductive through-holes through a dielectric layer.
    상세보기
  6. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
    상세보기
  7. Powell Jimmie L. (Wappingers Falls NY) Standley Charles L. (Hopewell Junction NY) Suierveld John (San Jose CA), Process for the controlled etching of tapered vias in borosilicate glass dielectrics.
    상세보기
  8. Weitze Artur (Munich DT) Sapunarow Michail (Munich DT), Process for the production of a multi-chip wiring arrangement.
    상세보기
  9. Bartlett Charles J. (Madison NJ) Rhodes Ronald J. (South Plainfield NJ) Rust Ray D. (Berkeley Heights NJ), Treating multilayer printed wiring boards.
    상세보기

이 특허를 인용한 특허 (52)

  1. Kazuo Miyajima JP; Shin Hasegawa JP; Yoshiaki Sawaki JP, Bus bar wiring board and method of producing the same.
    상세보기
  2. Alex Waizman IL; Chee-Yee Chung ; Bob Sankman, Chip package and method.
    상세보기
  3. Isaacs Phillip Duane ; Swain Miles Frank ; Mathison Connie Jean, Column grid array or ball grid array pad on via.
    상세보기
  4. Isaacs Phillip Duane ; Swain Miles Frank ; Mathison Connie Jean, Column grid array or ball grid array pad on via.
    상세보기
  5. Burdick, Jr.,William Edward; Rose,James Wilson; Tkaczyk,John Eric; Meirav,Oded; Arenson,Jerome Stephen; Hoffman,David Michael, Electronic packaging and method of making the same.
    상세보기
  6. Pasco Robert W. ; Reddy Srinivasa S. N. ; Vallabhaneni Rao V., Enhanced interconnection to ceramic substrates.
    상세보기
  7. Marrs Robert C., Integrated circuit chip to substrate interconnection.
    상세보기
  8. Marrs Robert C., Integrated circuit chip to substrate interconnection and method.
    상세보기
  9. Choi, A Leam; Lee, Kenny; Yoon, In Sang; Shin, HanGil, Integrated circuit packaging system with interposer interconnections and method of manufacture thereof.
    상세보기
  10. Osaki Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Sasaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Interboard connection terminal and method of manufacturing the same.
    상세보기
  11. Akram Salman, Interconnect for testing semiconductor components and method of fabrication.
    상세보기
  12. Kline, Jerry D., Interposer for improved handling of semiconductor wafers and method of use of same.
    상세보기
  13. Bischoff Peter G. ; Stovall Ross W, Interposer with embedded circuitry and method for using the same to package microelectronic units.
    상세보기
  14. Bolken, Todd O.; Corisis, David J., Interposers having encapsulant fill control features.
    상세보기
  15. Kline, Jerry D., Matched set of integrated circuit chips selected from a multi wafer-interposer.
    상세보기
  16. Leedy, Glenn, Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus.
    상세보기
  17. Kline, Jerry D., Method for constructing a wafer-interposer assembly.
    상세보기
  18. Kar-Roy, Arjun; Racanelli, Marco; Howard, David J., Method for fabricating a backside through-wafer via in a processed wafer and related structure.
    상세보기
  19. Akram,Salman; Farnworth,Warren M.; Wood,Alan G., Method for fabricating semiconductor components by forming conductive members using solder.
    상세보기
  20. Beatty Christopher C. (Ft. Collins CO), Method for forming tungsten structures in a semiconductor.
    상세보기
  21. Halahan, Patrick B., Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity.
    상세보기
  22. Kline, Jerry D., Method for manufacturing a wafer-interposer assembly.
    상세보기
  23. Dong Shin KR; Keon Yang Park KR; Young Hwan Shin KR; Byung Kook Sun KR; Jae Heun Joung KR, Method for manufacturing build-up multi-layer printed circuit board by using yag laser.
    상세보기
  24. Pierce,John L., Method for producing a wafer interposer for use in a wafer interposer assembly.
    상세보기
  25. Hanson David A., Method for reducing via inductance in an electronic assembly and article.
    상세보기
  26. Kline, Jerry D., Method for selecting components for a matched set from a wafer-interposer assembly.
    상세보기
  27. Iadanza, Joseph A., Method of connecting core I/O pins to backside chip I/O pads.
    상세보기
  28. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Method of making a flexible tester surface for testing integrated circuits.
    상세보기
  29. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Method of making and testing an integrated circuit.
    상세보기
  30. Osaka Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Susaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Method of manufacturing an interboard connection terminal.
    상세보기
  31. Miyazawa, Hiroyuki, Method of producing wiring substrate.
    상세보기
  32. Leedy Glenn J. (Santa Barbara CA), Method of repairing an integrated circuit structure.
    상세보기
  33. Leedy Glenn J., Method of repairing defective traces in an integrated circuit structure.
    상세보기
  34. Narasimhan, Swaminathan; Bessho, Koji, Methods and systems for controlling data acquisition system noise.
    상세보기
  35. Juskey ; Jr. Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL) Suppelsa Anthony B. (Coral Springs FL), Pad grid array for receiving a solder bumped chip carrier.
    상세보기
  36. Shen, Hong, Process for fabricating gallium arsenide devices with copper contact layer.
    상세보기
  37. Layher Francis W. (Tuscon AZ) Fulinara Napoleon (San Diego CA), Refurbishing of prior used laminated ceramic packages.
    상세보기
  38. Asai, Shuji; Hidaka, Tadachika; Kurosawa, Naoto; Oikawa, Hirokazu; Niwa, Takaki, Semiconductor apparatus.
    상세보기
  39. Kazuyoshi Furusawa JP, Semiconductor device.
    상세보기
  40. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Semiconductor package having interconnect with conductive members.
    상세보기
  41. Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
    상세보기
  42. Leedy, Glenn, System for probing, testing, burn-in, repairing and programming of integrated circuits.
    상세보기
  43. Anschel Morris (Wappingers Falls NY) Ormond Douglas W. (Wappingers Falls NY) Hayunga Carl P. (Poughkeepsie NY), Thin film metallization process for improved metal to substrate adhesion.
    상세보기
  44. Gregg J. Armezzani ; Kishor V. Desai ; Jeffrey S. Perkins ; John J. Pessarchick, Use of blind vias for soldered interconnections between substrates and printed wiring boards.
    상세보기
  45. Koyama Linda J. (Sunnyvale CA) Thomas Mammen (San Jose CA) Levinson Harry J. (San Jose CA), Via in a planarized dielectric and process for producing same.
    상세보기
  46. Pierce, John L., Wafer interposer assembly.
    상세보기
  47. Kline, Jerry D., Wafer level interposer.
    상세보기
  48. Caletka, David Vincent; Park, Seungbae; Sathe, Sanjeev Balwant, Wafer scale thin film package.
    상세보기
  49. Caletka,David Vincent; Park,Seungbae; Sathe,Sanjeev Balwant, Wafer scale thin film package.
    상세보기
  50. Kline, Jerry D., Wafer-interposer assembly.
    상세보기
  51. Pierce, John L., Wafer-interposer using a ceramic substrate.
    상세보기
  52. Higashiguchi Yutaka,JPX ; Inagaki Mitsuo,JPX ; Totani Makoto,JPX ; Teshima Yasuhiro,JPX ; Iimura Hiroshi,JPX, Wiring substrate and semiconductor device.
    상세보기

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