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A single-array memory employs a novel storage cell providing dual read/write access via either an “A”-side or a “B”-side. The storage cell uses a unique circuit in which read current is borrowed during writing into the cell. Asymmetrical read/write delay circuitry is provided to avoid overwriting th

A single-array memory employs a novel storage cell providing dual read/write access via either an “A”-side or a “B”-side. The storage cell uses a unique circuit in which read current is borrowed during writing into the cell. Asymmetrical read/write delay circuitry is provided to avoid overwriting the contents of a storage cell during the read-to-write transition. Row-selection decoders use Schottky-clamping diodes in a way which provide an equivalent oscillation-damping capacitance at the base of the selected-row driver transistor. The single-array memory can be advantageously used as part of a single-chip VLSI four-port register file permitting simultaneous reading and/or writing of registers from any of two read ports or two write ports, respectively. Unidirectional busses connect each storage cell to each of the four ports.

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In a dual-access read/write digital storage device having at least two input port means for receiving plural-bit data words, at least two output port means for generating plural-bit data words, dual-access read/write random access memory (RAM) means having a plurality of addressable registers each s

In a dual-access read/write digital storage device having at least two input port means for receiving plural-bit data words, at least two output port means for generating plural-bit data words, dual-access read/write random access memory (RAM) means having a plurality of addressable registers each storing one of said plural-bit data words said RAM means responsive to a first and a second storage register address signal and to a first and a second bi-state read/write signal for coupling said RAM storage register having said first address to a first predetermined one of said input port means or to a first predetermined one of said output port means depending on the state of said first read/write signal and for coupling said RAM storage register having said second address to a second predetermined one of said input port means or to a second predetermined one of said output port means depending on the state of said second read/write signal, whereby, the plural-bit contents of said RAM register selected by said first, said second address signals, respectively, can be communicated to a predetermined one, a predetermined second, respectively, of said at least two output port means and/or replaced by said plural-bit data word at a predetermined one, a predetermined second, respectively, of said at least two input port means.