초록 ▼

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a fir

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

대표청구항 ▼

A circuit, integrable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including: first and second voltage input terminals, first and second positive transfer capacitor connection ter

A circuit, integrable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including: first and second voltage input terminals, first and second positive transfer capacitor connection terminals, a first set of MOS semiconductor switches for selectively connecting said first voltage input terminal to said first and second positive transfer capacitor connection terminal and said second voltage input terminal to said second positive transfer capacitor connection terminal, first and second positive reservoir capacitor connection terminals, a second set of MOS semiconductor switches for selectively connecting said first voltage input terminal to said second positive transfer capacitor connection terminal and for selectively connecting said second voltage input terminal to said first positive reservoir capacitor connection terminal and said first positive transfer capacitor connection terminal to said second positive reservoir capacitor connection terminal, first and second negative transfer capacitor connection terminals, a third set of MOS semiconductor switches for selectively connecting said first positive reservoir capacitor connection terminal to said first negative transfer capacitor connection terminal and said second positive reservoir capacitor connection terminal to said second negative transfer capacitor connection terminal, first and second negative reservoir capacitor connection terminals, said first negative reservoir capacitor connection terminal connected to said first positive reservoir capacitor connection terminal, a fourth set of MOS semiconductor switches for selectively connecting said first negative transfer capacitor connection terminal to said second negative reservoir capacitor connection terminal and said second negative transfer capacitor connection terminal to said first negative reservoir capacitor connection terminal, selection circuitry for selectively activating said first, second, third and fourth sets of MOS semiconductor switches, means for clamping said second positive reservoir capacitor terminal to a voltage approximately equal to the voltage appearing on said first voltage input terminal, means for clamping said second negative reservoir capacitor to a voltage approximately equal to the voltage appearing on said second voltage input terminal, means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.