초록 ▼

The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are

The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET\s. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels. Further, the GTLM structure may be implemented in any existing semiconductor FET technology, including silicon, GaAs, and modulation-doped structures.

대표청구항 ▼

A gated transmission line model TLM pattern for use in field-effect transistor characterization, comprising: a semiconductor substrate having a major surface which has a conducting channel of uniform width formed into and along a region on said surface; a plurality of at least four spaced ohmic cont

A gated transmission line model TLM pattern for use in field-effect transistor characterization, comprising: a semiconductor substrate having a major surface which has a conducting channel of uniform width formed into and along a region on said surface; a plurality of at least four spaced ohmic contacts deposited on the substrate surface at and along said conducting channel region; wherein a first space between a first and a second of said ohmic contacts is a different dimension from a second space between the second and a third of said ohmic contacts, and a third space between said third and fourth of said ohmic contacts is a different dimension from the first and second spaces; a plurality of at least three Schottky metal gates deposited on said surface, one gate being deposited, respectively, in each of said spaces between the plurality of ohmic contacts, the dimension of the gate being smaller than the dimension of the space it is in to establish a gate-to-ohmic spacing, whereby the plurality of Schottky metal gates includes a first, a second and a third gate positioned in said first, second and third spaces, respectively, with the length of each of said gates being x (where x is a number) microns smaller than the dimension of the related space so that the gate-to-ohmic spacing remains the same in each of said spaces.