초록 ▼

One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges betwe

One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

대표청구항 ▼

1. An assembly comprising a wafer having top and bottom surfaces, said top surface constituting a planar uppermost surface of said wafer and said bottom surface constituting a planar bottommost surface of said wafer, said wafer having conductive terminal portions on said top surface, at least on

1. An assembly comprising a wafer having top and bottom surfaces, said top surface constituting a planar uppermost surface of said wafer and said bottom surface constituting a planar bottommost surface of said wafer, said wafer having conductive terminal portions on said top surface, at least one microminiature device mounted on the top surface of said wafer, said device having a top surface and including conductive elements in a central portion of the top surface of said device, each device mounted on the top surface of said wafer having at least one sloped edge extending from said central portion toward the top surface of said wafer, and a conductive pattern connecting the elements of each device mounted on the top surface of said wafer to said terminal portions, said pattern being disposed entirely on the sloped edge of each device and on the top surface of said wafer. 2. An assembly as in claim 1 wherein said at least one microminiature device comprises an integrated circuit device including a monocrystalline silicon chip. 3. An assembly as in claim 2 wherein the top and bottom surfaces of said silicon chip lie in (100) crystalline planes. 4. An assembly as in claim 3 wherein said at least one sloped edge lies in a (111) crystalline plane of said silicon chip. 5. An assembly as in claim 4 wherein an adhesive layer is interposed between each device and said wafer. 6. An assembly as in claim 1 wherein said wafer includes additional conductive terminal portions on said bottom surface, at least one microminiature device mounted on the bottom surface of said wafer, said device having an unmounted surface and including conductive elements in a central portion of its unmounted surface, each device mounted on the bottom surface of said wafer having at least one sloped edge extending from its central portion toward the bottom surface of said wafer, and a conductive pattern connecting the elements of a device mounted on the bottom surface of said wafer to said additional terminal portions, said pattern being disposed entirely on the sloped edge of each device mounted on the bottom surface of said wafer and on the planar bottom surface of said wafer. 7. A method of fabricating an assembly that comprises a wafer and at least one wafer-mounted microminiature device that includes conductive elements in a central portion of the active surface of the device, the wafer having planar top and bottom surfaces, said method comprising the steps of mounting said at least one device, active side up, on the top surface of said wafer, forming at least one sloped edge on said mounted device extending from the central portion of said device toward the top surface of said wafer, and forming a conductive pattern overlying the top surface of said wafer and said sloped edge to connect the elements of said mounted device to conductive elements on at least one other wafer-mounted device and to peripherally disposed terminal portions of said conductive pattern. 8. A method as in claim 7 wherein said at least one microminiature device comprises an integrated circuit device including a monocrystalline silicon chip. 9. A method as in claim 8 wherein the top and bottom surfaces of said silicon chip lie in (100) crystalline planes. 10. A method as in claim 9 wherein said forming step comprises etching peripheral portions of said at least one silicon chip to establish said at least one sloped edge in a (111) crystalline plane of said chip. 11. A method as in claim 10 wherein the central portion of said at least one silicon chip is protected with an etch-resistant layer of silicon nitride and etching is carried out with an anisotropic etch such as a potassium hydroxide solution. 12. A method as in claim 11 wherein, subsequent to etching, said etch-resistant layer is removed. 13. A method as in claim 12 wherein an insulating layer is next deposited over the entire top surface of said assembly. 14. A method as in claim 13 wherein said insulating layer is patterned to form openings therethrough in respective registry with said conductive elements. 15. A method as in claim 14 wherein a patterned conductive layer is formed overlying said insulating layer and in said openings to form said peripherally disposed terminal portions and a network of leads interconnecting said elements and said terminal portions. 16. A method as in claim 7 wherein during said mounting and forming steps at least one sloped-edge microminiature device with centrally positioned conductive elements is mounted, active side down, on the bottom side of said wafer and connections are established from said last-mentioned elements to conductive elements on at least one other bottom-mounted device and to peripherally disposed terminal portions of a conductive pattern formed overlying the bottom side of said wafer. 17. A method as in claim 16 wherein connections are also established between conductive elements and terminal portions on one side of said wafer and conductive elements and terminal portions on the other side of said wafer. 18. An assembly made by the method of claim 7. 19. An assembly as in claim 18 wherein each of said wafer-mounted devices includes circuits formed in the central portion of the top surface of the device, and wherein said conductive pattern includes a signal conduit path and a plurality of arbitration conduit paths, a plurality of the devices being coupled to said signal conduit path and selectively needing to transmit information onto said signal conduit path, the wafer and at least some of said devices being of essentially the same material, wherein each of the devices is adapted to have a priority with respect to transmission of information onto the signal conduit path, wherein each of the devices, comprises a separate one of a plurality of arbitration request circuits, wherein each arbitration request circuit is coupled to a separate one of the arbitration conduit paths and is adapted to selectively allow a signal from its device to reach the arbitration signal conduit path coupled thereto, wherein each of the devices, comprises a separate one of a plurality of arbitration circuits, and wherein each arbitration circuit is coupled to at least one of the arbitration conduit paths and is adapted to detect which of any of the other devices having a higher priority is requesting access to the signal conduit path and to enable its device to gain access to the signal conduit path if its device is requesting access to the signal conduit path and if its device has a higher priority than any other device which is requesting such access.