초록

A decoder circuit for MOS memory of a redundant structure having shorter delays in access time contains a programmable element in a redundant circuit rather than connected in series on the word line driving signal.

대표청구항 ▼

A decoder circuit for MOS memory, said MOS memory having a redundant structure, comprising a word line, first MOS transistors for word line selection, an output line connected to said first MOS transistors in common, a second MOS transistor, the transmissive/non-transmissive condition thereof being

A decoder circuit for MOS memory, said MOS memory having a redundant structure, comprising a word line, first MOS transistors for word line selection, an output line connected to said first MOS transistors in common, a second MOS transistor, the transmissive/non-transmissive condition thereof being controlled by the precharge voltage of said output line to control the transmission of output signals to said word line, a third MOS transistor for maintaining voltage, and a control circuit including a programmable element which can be in transmissive or non-transmissive condition, said control circuit serving to form an output signal such that said third MOS transistor is maintained in non-transmissive condition if said programmable element is in transmissive condition and that said third MOS transistor is made transmissive if said programmable element is in non-transmissive condition, said third MOS transistor having a drain connected to said output line, a source connected to ground potential and a gate connected to said control circuit.