초록 ▼

Two intermediate potentials of small current driving capacity are generated using load elements and MOS transistors, and are respectively supplied to the gates of two MOS transistors which are series-connected between power sources and have large current driving capacity, thus obtaining an intermedi

Two intermediate potentials of small current driving capacity are generated using load elements and MOS transistors, and are respectively supplied to the gates of two MOS transistors which are series-connected between power sources and have large current driving capacity, thus obtaining an intermediate potential from a node between the MOS transistors. The MOS transistors at the output stage are complementarily operated so as not to be turned on at the same time.

대표청구항 ▼

An intermediate potential generation circuit, comprising: a first potential supply source; a first load element, one end of which is connected to said first potential supply source; a first MOS transistor of a first conductivity type, one end and a gate of which are connected to the other end of sai

An intermediate potential generation circuit, comprising: a first potential supply source; a first load element, one end of which is connected to said first potential supply source; a first MOS transistor of a first conductivity type, one end and a gate of which are connected to the other end of said first load element; a second MOS transistor of a second conductivity type, one end of which is connected to the other end of said first MOS transistor; a second load element, one end of which is connected to the other end and a gate of said second MOS transistor; a second potential supply source connected to the other end of said second load element; a third MOS transistor of the first conductivity type having one end connected to said first potential supply source and a gate connected to a node between said first load element and said first MOS transistor; a fourth MOS transistor of the second conductivity type connected between the other end of said third MOS transistor and said second potential supply source, and having a gate connected to a node between said second MOS transistor and said second load element; and an output terminal, connected to a node between said third and fourth MOS transistors, for generating an intermediate potential between said first and second potential supply sources.