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Method for planarizing semiconductor substrates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B44C-001/22
  • B29C-037/00
  • C03C-015/00
  • C03C-025/06
출원번호 US-0855207 (1986-04-23)
발명자 / 주소
  • Riley Paul E. (San Jose CA) Ray Alan B. (Palo Alto CA) Bayer Paul (San Jose CA)
출원인 / 주소
  • Fairchild Semiconductor Corporation (Cupertino CA 02)
인용정보 피인용 횟수 : 47  인용 특허 : 7

초록

A method for planarizing an insulating layer overlying an irregular topographic substrate, e.g., a conductive layer, is planarized by use of a sacrificial planarization layer. The planarization layer is removed using an oxygen-containing plasma generated in a parallel electrode reactor operating at

대표청구항

A method for planarizing an insulating layer and exposing underlying topographic features, said method comprising: applying a planarization layer over the insulating layer to thickness sufficient to form a substantially level surface; uniformly etching the planarization layer with a first plasma dow

이 특허에 인용된 특허 (7)

  1. Chen Lee (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Control of etch rate ratio of SiO2/photoresist for quartz planarization etch back process.
  2. Otsubo Toru (Fujisawa JPX) Aiuchi Susumu (Yokohama JPX) Kamimura Takashi (Yokohama JPX), Etching method and apparatus.
  3. Sobczak Zbigniew P. (Colorado Springs CO), Formation and planarization of silicon-on-insulator structures.
  4. Groves Christopher K. (Bromont VT CAX) Duncan Kevin (St. Albans VT) Darwall Edward C. D. (Bromont CAX), Integrated circuit planarizing process.
  5. Moriya Takahiko (Yokosuka JPX) Hazuki Yoshikazu (Yokohama JPX) Kashiwagi Masahiro (Fujisawa JPX), Method for producing semiconductor device.
  6. Silverman Peter J. (Palo Alto CA), Method for sloping insulative layer in bubble memory.
  7. Barton, Donald L., Planarization of dielectric films on integrated circuits.

이 특허를 인용한 특허 (47)

  1. Babu, Suryadevara V.; Amanapu, Hariprasad; Laguda, Uma Rames Krishna; Teki, Ranganath, Abrasive-free planarization for EUV mask substrates.
  2. Savage Richard N. (Livermore CA), Apparatus and method for automatically identifying chemical species within a plasma reactor environment.
  3. Riley Paul E. (Columbia MD) Kulkarni Vivek D. (Sunnyvalle CA) Castel Egil D. (Cupertino CA), Etch back detection.
  4. Meng, Lingkkuan; Yin, Huaxiang, Etch-back method for planarization at the position-near-interface of an interlayer dielectric.
  5. Wang Wen-chou Vincent ; Peters Michael G. ; Zhou Dashun S. ; Takahashi Yasuhito, Flip chip pre-assembly underfill process.
  6. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
  7. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
  8. Okabe Naoto,JPX ; Iida Makio,JPX ; Tokura Norihito,JPX, Insulated gate type field effect transistor and method of manufacturing the same.
  9. Otani, Miharu; Tanaka, Jun; Masuda, Kazuhito; Adachi, Masaya; Hiratsuka, Takato, Liquid crystal display device and method of manufacturing the same.
  10. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
  11. Wong,William S.; Kneissl,Michael A.; Teepe,Mark, Method for controlling the structure and surface qualities of a thin film and product produced thereby.
  12. Suwa,Takahiro; Hattori,Kazuhiro; Okawa,Shuichi; Hibi,Mikiharu, Method for filling concave portions of concavo-convex pattern and method for manufacturing magnetic recording medium.
  13. Mizukoshi, Masataka; Ishizuki, Yoshikatsu; Nakagawa, Kanae; Okamoto, Keishiro; Teshirogi, Kazuo; Sakai, Taiji, Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus.
  14. Hattori,Kazuhiro; Okawa,Shuichi; Suwa,Takahiro; Hibi,Mikiharu, Method for manufacturing a magnetic recording medium.
  15. Hattori,Kazuhiro; Okawa,Shuichi; Suwa,Takahiro; Hibi,Mikiharu, Method for manufacturing magnetic recording medium.
  16. Roth Scott S. (Austin TX) Ray Wayne J. (Austin TX) Kirsch Howard C. (Austin TX), Method for planarizing a layer of material.
  17. Abraham Thomas (Kanata ; Ontario CAX), Method for planarizing an insulating layer.
  18. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
  19. Zdebel Peter J. (Mesa AZ), Method of forming semiconductor structure isolation regions.
  20. Villalon Claudine (Chennevieres FRX), Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at d.
  21. Ishibashi Takeo,JPX, Method of manufacturing semiconductor device having multilayer interconnection structure.
  22. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
  23. Palmour John W. (Raleigh NC) Kong Hua-Shuang (Raleigh NC) Edmond John A. (Apex NC), Method of preparing silicon carbide surfaces for crystal growth.
  24. Zeto Robert J. (Eatontown NJ) Hryckowian ; deceased Eugene (late of Ocean NJ by Linda V. ; executor) Morton David C. (Eatontown NJ) Costello John A. (Annapolis MD) Conrad John C. (Ocean NJ), Method of smoothing patterned transparent electrode stripes in thin film electroluminescent display panel manufacture.
  25. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
  26. Bothra Subhas ; Weling Milind G., Optimized underlayer structures for maintaining chemical mechanical polishing removal rates.
  27. Sreenivasan, Sidlgata V.; Schumaker, Philip D., Patterning a plurality of fields on a substrate to compensate for differing evaporation times.
  28. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Patterning substrates employing multiple chucks.
  29. Sato Takashi,JPX ; Okumura Katsuya ; Iba Junichiro, Planarization method and system using variable exposure.
  30. Takashi Sato JP; Katsuya Okumura ; Junichiro Iba, Planarization method and system using variable exposure.
  31. Brooks Garth A. (Wappingers Falls NY) Greco Nancy A. (Lagrangeville NY), Planarization process through silylation.
  32. Brooks Garth A. (Wappingers Falls NY) Greco Nancy A. (Lagrangeville NY), Planarization through silylation.
  33. Sung Hung-Cheng,TWX ; Chen Ling, Planarized plug-diode mask ROM structure.
  34. Kamijima, Akifumi; Yatsu, Hideyuki; Hatate, Hitoshi, Planarizing method.
  35. Chan-lon Yang ; Usha Raghuram ; Kimberley A. Kaufman ; Daniel Arnzen ; James Nulty, Plasma etching method.
  36. Guinn Keith V. ; McNevin Susan Clardy, Process for device fabrication in which the plasma etch is controlled by monitoring optical emission.
  37. Nishida Shoji (Nagahama JPX), Process for the formation of a silicon-containing semiconductor thin film by chemically reacting active hydrogen atoms w.
  38. Schmid, Gerard M.; Stacey, Nicholas A; Resnick, Douglas J.; Voisin, Ronald D.; Myron, Lawrence J., Self-aligned process for fabricating imprint templates containing variously etched features.
  39. Kneafsey, Brendan J.; Guthrie, John; Coughlan, Gerard, Semi-solid one- or two-part compositions.
  40. Matsubara Junko,JPX ; Tajima Toru,JPX ; Harada Shigeru,JPX, Semiconductor device and method of manufacturing thereof.
  41. Tanaka, Junji, Semiconductor device having a semiconductor chip mounted on an insulator film and coupled with a wiring layer, and method for manufacturing the same.
  42. Chew Peter,SGX, Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrat.
  43. Sreenivasan, Sidlgata V.; Choi, Byung J.; Schumaker, Norman E.; Voisin, Ronald D.; Watts, Michael P. C.; Meissl, Mario J., Step and repeat imprint lithography processes.
  44. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
  45. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
  46. Sreenivasan, Sidlgata V.; Schumaker, Philip D.; McMackin, Ian M., Tessellated patterns in imprint lithography.
  47. Choi,Nack Bong; Nam,Seung Hee; Oh,Jae Young, Two step maskless exposure of gate and data pads.
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