초록 ▼

A hierarchical configurable gate array is disclosed and includes a plurality of cluster regions (10,20,30,40) arranged in different levels. The first level cluster (10) includes an integral number N multi-terminal components for providing canonical functions. The second level cluster (20) includes N

A hierarchical configurable gate array is disclosed and includes a plurality of cluster regions (10,20,30,40) arranged in different levels. The first level cluster (10) includes an integral number N multi-terminal components for providing canonical functions. The second level cluster (20) includes N first level clusters; and higher level clusters (30,40) each includes N clusters of the next lower level. Interconnect regions (13,15,17,19) are provided within each cluster for interconnections between the N elements of each level. Selected input or output ports for each element of a cluster are available for interconnection at more than one location.

대표청구항 ▼

An hierarchical gate array comprising: at least three clusters of increasing level and size, each cluster having logic gates grouped in a plurality of cluster elements where the number of gates in a cluster increases with cluster level; respective interconnect regions within each cluster for accommo

An hierarchical gate array comprising: at least three clusters of increasing level and size, each cluster having logic gates grouped in a plurality of cluster elements where the number of gates in a cluster increases with cluster level; respective interconnect regions within each cluster for accommodating selected interconnections between cluster elements, said selected interconnections defining respective cluster functions for each said cluster and said interconnect regions having respective areas related to the respective number of gates in respective clusters; respective input/output means located about the periphery of each cluster for providing access to the cluster functions of respective cluster regions; and wherein each higher level cluster above the first level cluster includes as its cluster elements a plurality of lower level clusters separated by a respective interconnect region which accommodates interconnections between the respective input/output means of said lower level clusters.