초록 ▼

Disclosed is a data detection system and method for accurately detecting data transition marks recorded on a recording surface. A data transition pulse, generated by a data head as recorded data transition marks pass thereby, is presented to consecutive delay circuits in order to generate first and

Disclosed is a data detection system and method for accurately detecting data transition marks recorded on a recording surface. A data transition pulse, generated by a data head as recorded data transition marks pass thereby, is presented to consecutive delay circuits in order to generate first and second delay pulses. The second delay pulse and the data transition pulse are subtracted from the first delay pulse, thereby creating a narrow output pulse that indicates the occurrence of a data transition. This narrow output pulse is used to toggle a flip-flop or equivalent logic circuit, the flip-flop output thereby representing a recreation of the data as recorded on the recording surface. The system is best suited for use with an optical storage system wherein data transitions are recorded on an optical disk as spots of substantially uniform size, although the detection system does not require that the spots be uniform size.

대표청구항 ▼

A data detection system for detecting the spacing between data transition marks recorded on a recording surface, said system comprising; a data head positioned to sense said data transition marks, said data head including means for generating a data transition signal whenever one of said data transi

A data detection system for detecting the spacing between data transition marks recorded on a recording surface, said system comprising; a data head positioned to sense said data transition marks, said data head including means for generating a data transition signal whenever one of said data transition marks passes by said head; means for creating relative motion between said data head and said recording surface, whereby selected data transition marks pass by said head; first delay means for generating a first delayed data transition signal that comprises said data transition signal delayed by a first prescribed time; second delay means for generating a second delayed data transition signal that comprises said data transition signal delayed by a second prescribed time; an input stage through which said data transition signal passes prior to being presented to said first delay means, said input stage serving to buffer said data transition signal prior to delaying it with said first and second delay means; signal combining means for subtracting said data transition signal and said second delayed data transition signal from said first delayed data transition signal in order to generate a data transition pulse signal; and means responsive to said data transition pulse signal for changing the level or state of a logic data signal, whereby said logic data signal changes status in response to each data transition mark that passes by said head, said data logic signal thereby being representative of the data recorded on said recorded surface as detected by said data head.