초록 ▼

An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as p

An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

대표청구항 ▼

A method of fabricating an improved chip carrier having a ceramic base providing a hermetically-sealed package, the method comprising the steps of: preparing the ceramic base, which consists of a single prefired ceramic substrate having a top major surface and a bottom major surface and which has an

A method of fabricating an improved chip carrier having a ceramic base providing a hermetically-sealed package, the method comprising the steps of: preparing the ceramic base, which consists of a single prefired ceramic substrate having a top major surface and a bottom major surface and which has an array of conductive through holes, each through-hole surrounded by conductors on both top and bottom major surfaces and plugged by solder plugs substantially therethrough other than on the top surface, so as to electrically connect, via a plurality of conductive runners that outwardly extend on the top surface, to an arrangement of pads near the periphery of the top surface thereof; and preparing a single, flexible dielectric slip for placing as a solid sheet on and affixing to said single, pre-fired ceramic substrate, within the arrangement of pads, for covering said array of through-holes plugged by solder plugs substantially therethrough other than on the top surface as well as a portion of said plurality of conductive runners, and having a top surface for affixing a semiconductor chip, said single, flexible dielectric slip providing an insulated die mount pad as well as a dielectric layer for the semiconductor chip to allow utilization of the area therebeneath for said plurality of conductive runners and said solder-plugged through-holes forming a pad array interface on the bottom surface of said single, prefired ceramic substrate as well as providing a hermetic seal for each through-hole therein, thereby providing a hermetically-sealed, ultra high density pad array chip carrier which is able to accommodate a wide variety of semiconductor chips.