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Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward s 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0790570 (1985-10-23)
발명자 / 주소
  • Lee Ruby B. (Cupertino CA) Mahon Michael J. (San Jose CA)
출원인 / 주소
  • Hewlett-Packard Company (Palo Alto CA 02)
인용정보 피인용 횟수 : 41  인용 특허 : 0

초록 ▼

A computer and an instruction set are presented which allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although an assist\s o

대표청구항 ▼

A computing device, comprising: a bus which carries data; an assist, which can be coupled to the bus and which can be uncoupled from the bus, including a first functional means for executing an assist instruction; a main processor, coupled to the bus, including a second functional means for executin

이 특허를 인용한 특허 (41)

  1. Wilhelm Neil C. (Menlo Park CA) Leonard Judson S. (Waban MA), Apparatus and method for a pipelined central processing unit in a data processing system.
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  2. Wilhelm Neil C. (Menlo Park CA) Leonard Judson S. (Waban MA), Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit.
    상세보기
  3. Winter Marco,DEX, Apparatus for processing a sequence of control commands as well as a method for generating a sequence of control commands, and storage medium for storing control commands.
    상세보기
  4. Adams,Phillip M., CPU life-extension apparatus and method.
    상세보기
  5. Nakayama Takashi (Tokyo JPX), Coprocessor having a slave processor capable of checking address mapping.
    상세보기
  6. Morris,Chris, Data processor with enhanced instruction execution and method.
    상세보기
  7. Nagaraj Ravi ; Solomon Gary A., Device to assist software emulation of hardware functions.
    상세보기
  8. Hum, Herbert; Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  9. Hum, Herbert; Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  10. Hum, Herbert; Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  11. Hum, Herbert; Sprangle, Eric; Carmean, Douglas; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  12. Hum, Herbert; Sprangle, Eric; Carmean, Douglas; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  13. Hum, Herbert; Sprangle, Eric; Carmean, Douglas; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  14. Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Distribution of tasks among asymmetric processing elements.
    상세보기
  15. Blomgren James S. ; Richter David E., Dual-instruction-set architecture CPU with hidden software emulation mode.
    상세보기
  16. Luk, Wayne; Cheung, Peter Y. K.; Seng, Shay Ping, Flexible instruction processor systems and methods.
    상세보기
  17. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Generating hardware accelerators and processor offloads.
    상세보기
  18. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Hardware accelerator test harness generation.
    상세보기
  19. Thusoo Shalesh (Milpitas CA) Sajjadian Farnad (Sunnyvale CA) Kohli Jaspal (Sunnyvale CA) Patkar Niteen A. (Sunnyvale CA), Hardware support for fast software emulation of unimplemented instructions.
    상세보기
  20. Latta, David, Memory interface and method of interfacing between functional entities.
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  21. Latta, David, Memory interface and method of interfacing between functional entities.
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  22. Latta, David, Memory interface and method of interfacing between functional entities.
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  23. Priem Curtis (Fremont CA) Malachowsky Chris (Santa Clara CA) McIntyre Bruce (Cupertino CA) Moffat Guy (Palo Alto CA), Method and apparatus for allowing computer circuitry to function with updated versions of computer software.
    상세보기
  24. Moyer,William C.; Arends,John; Scott,Jeffrey W., Method and apparatus for interfacing a processor to a coprocessor.
    상세보기
  25. Hakewill,James Robert Howard; Sanders,John, Method and apparatus for jump control in a pipelined processor.
    상세보기
  26. Hakewill, James Robert Howard; Khan, Mohammed Noshad; Plowman, Edward, Method and apparatus for managing the configuration and functionality of a semiconductor design.
    상세보기
  27. Talati Kiritkumar (Sunnyvale TX) Lackie C. Willard (Richardson TX), Method for providing a virtual execution environment on a target computer using a virtual software machine.
    상세보기
  28. Fuhler, Richard A.; Pennello, Thomas J.; Jalkut, Michael Lee; Warnes, Peter, Methods and apparatus for compiling instructions for a data processor.
    상세보기
  29. Fuhler,Richard A.; Pennello,Thomas J.; Jalkut,Michael Lee; Warnes,Peter, Methods and apparatus for compiling instructions for a data processor.
    상세보기
  30. Barry, Edwin F.; Pechanek, Gerald G.; Strube, David Carl, Methods and apparatus for providing context switching between software tasks with reconfigurable control.
    상세보기
  31. Barry,Edwin Franklin; Pechanek,Gerald George; Strube,David, Methods and apparatus for providing context switching between software tasks with reconfigurable control.
    상세보기
  32. Hum, Herbert; Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state.
    상세보기
  33. Jahagirdar, Sanjeev S.; George, Varghese; Sodhi, Inder, Migrating threads between asymmetric cores in a multiple core processor.
    상세보기
  34. Scalzi Casper Anthony ; Schwarz Eric Mark ; Starke William John ; Urquhart James Robert ; Westcott Douglas Wayne, Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatibl.
    상세보기
  35. Cumplido,Rene; Goodall,Roger; Jones,Simon, Processor apparatus and methods optimized for control applications.
    상세보기
  36. Wang, Perry; Collins, Jamison; Wang, Hong, Processor for enabling inter-sequencer communication following lock competition and accelerator registration.
    상세보기
  37. Annicchiarico Richard Francis ; Chesler Robert Todd ; Jamison Alan Quentin, Server extension for a computer system.
    상세보기
  38. Blomgren James S. (San Jose CA) Richter David E. (Milpitas CA) Brashears Cheryl Senter (Cupertino CA), Shared floating-point registers and register port-pairing in a dual-architecture CPU.
    상세보기
  39. Nunomura Yasuhiro (Itami JPX), Software trap system which saves previous content of software trap handling pointer in a stack upon execution of a trap.
    상세보기
  40. De Oliveira Kastrup Pereira, Bernardo; Bink, Adrianus J.; Hoogerbrugge, Jan, System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time.
    상세보기
  41. Hum, Herbert; Sprangle, Eric; Carmean, Doug; Kumar, Rajesh, Systems and methods for migrating processes among asymmetrical processing cores.
    상세보기

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