[특허]Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction proces

Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction proces 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/38
출원번호	US-0896156 (1986-08-18)
발명자 / 주소	Chuang Chiao-Mei (Briarcliff Manor NY)
출원인 / 주소	International Business Machines Corp. (Armonk NY 02)
인용정보	피인용 횟수 : 88 인용 특허 : 0

초록 ▼

Performance of a VLSI processor of the reduced instruction set computer (RISC) type is enhanced by executing two instructions simultaneously in the two execution units of the processor. There is very little increase in the cost of hardware. Three embodiments are presented with different cost and performance capabilities. The first embodiment has an instruction input to an instruction buffer (10) and two sets of control ROSs (40 and 42) and control registers (64 and 65). The control ROS and control register which is chosen depends on which instruction execution unit is to execute the instruction. Data inputs to the execution units is from a register file (48) which has an additional pair of outputs (51) and (53) that provide the data paths for simultaneous execution of instructions by the execution units. Execution unit I has an arithmetic and logic unit (ALU) (24), while execution unit II has a rotate (26) and mask generator (31). Load balancing between the two execution units can be performed by adding a multiplier (60) and divider (62) to execution unit II. In the second embodiment, additionally, load balancing is achieved by incorporating an adder (78) into execution unit II. The adder (78) is used to perform address calculations to speed up the load, store and branch instructions. In the third embodiment, an additional ALU (90) is added to execution unit II to allow the instruction processing to be further balanced between the two execution units.

대표청구항 ▼

In a reduced instruction set computer processing system having instruction handling apparatus comprising an instruction buffer, control read only storage and control registers, an adder for calculating an instruction address and instruction execution apparatus comprising a register file having inputs and outputs, one of said inputs being connected to receive data from memory, staging registers connected to said outputs, and first and second execution units, said first execution unit comprising an arithmetic logic unit having inputs connected to two of said staging registers, said second execution unit comprising a rotator and mask generator means having inputs connected to three of said staging registers, said arithmetic logic unit and said rotator and mask generator means having outputs, a first output register for receiving the outputs of said arithmetic logic unit or said rotator and mask generator means and supplying an input to said register file wherein the system performs sequential data manipulations under the control of instructions, said instructions being executed by one of said first and second execution units, the improvement which increases the throughput of the computer comprising: said control read only storage comprising first and second segments for respectively storing instruction sets for said first and second execution units; said instruction handling apparatus further including means for routing instructions from said first segment of said control read only storage to said first execution unit and means for routing instructions from said second segment of said control read only storage to said second execution unit; said adder being in said second execution unit and having inputs connected to two of said three of said staging registers; a multiplexer in said second execution unit connected to receive outputs from said adder and said rotate and mask generator means; a second output register, the outputs from said arithmetic logic unit and said multiplexer being separately connected to a respective one of said output registers, outputs from each of said first and second output registers being connected to inputs of said register file; and said first execution unit and said second execution unit simultaneously receiving outputs from staging registers connected to outputs of said register file and executing in parallel.

이 특허를 인용한 특허 (88)

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Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction proces 원문보기

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Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction proces 원문보기

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연구과제 타임라인

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