ECM preprocessor or tracker using multi-processor modules
원문보기
IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0880242
(1986-06-30)
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발명자
/ 주소 |
- Dunne, Timothy
- Gentry, James F.
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출원인 / 주소 |
- The United States of America as represented by the Secretary of the Air Force
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대리인 / 주소 |
Franz, Bernard E.Singer, Donald J.
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인용정보 |
피인용 횟수 :
5 인용 특허 :
8 |
초록
▼
The tracking apparatus uses multi-processor modules for predicting in real time the parametric behaviour of radar signals to be jammed, as part of an electronic countermeasures system. The tracker system is partitioned into three board (module) types--(1) a subsystem request handler, which transfers
The tracking apparatus uses multi-processor modules for predicting in real time the parametric behaviour of radar signals to be jammed, as part of an electronic countermeasures system. The tracker system is partitioned into three board (module) types--(1) a subsystem request handler, which transfers data from system buses to the tracker system, (2) one or more multi-processor modules (each including a parameter memory and three arithmetic units with micro-sequencers) which does the actual track operation yielding the prediction data, and (3) a vector buffer module, which transfers the completed prediction data onto the buses for the receiver and transmitter. The system computer transfers to the tracker the necessary parameter information (latest time of arrival, threat type (stable, stagger, agile, etc.), angle of arrival, etc.) and initiates a track loop. Central to the operation of the trackers is the parameter memory which is divided conceptually into two main parts: pattern and parameters. The parameter portion of the memory is subdivided into blocks, each dedicated to a particular threat. The defining parameters for that threat are passed from the CPU just before a tracker is started. Also stored as part of this parameter block will be a word providing starting addresses for the type of calculation (stable, agile, stagger, etc.) to be run for that parameter.
대표청구항
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1. A preprocessor unit for use in a multiprocessor system having bus means, for processing data from a plurality of sources, said preprocessor unit comprising: control means used as a subsystem request handler, including an input buffer and a system interface, which provides means for inputting a
1. A preprocessor unit for use in a multiprocessor system having bus means, for processing data from a plurality of sources, said preprocessor unit comprising: control means used as a subsystem request handler, including an input buffer and a system interface, which provides means for inputting address and data information from the bus means, when the address information includes a "name" designating said preprocessor unit; processing means including parameter memory means and arithmetic means, the arithmetic means comprising a plurality of chip sets, each chip set comprising an arithmetic unit and a micro-sequencer individually associated with that arithmetic unit, providing each arithmetic unit with its own independent microcontrol memory and controller, so that job timing and microprogram sequencing is independent for each arithmetic unit; and an output buffer used as a vector buffer, which provides means for outputting processed data onto the bus means; internal coupling means for coupling addresses and data from said control means to each of the micro-sequencers and the parameter memory means, for coupling data from the parameter memory means to each of the arithmetic units, from each of the arithmetic units to the parameter memory means, and from the arithmetic units to the output buffer; the parameter memory means being subdivided into blocks, said control means having microcode for designating a block of memory for a particular source, designating addresses for storing each of a plurality of parameters at a particular location in the block used for that source at an offset location relative to a starting location of the block.
이 특허에 인용된 특허 (8)
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Overman Thelma L. (Millers MD) Overman Kelly C. (Millers MD), Adaptive radar threat detection and tracker verification system.
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Evans Norol T. (San Pedro CA) Nelson Robert B. (Anaheim CA), Automatic ECM video processor.
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Pringle Robert D. (Severna Park MD) O\Berry William A. (Severna Park MD), Automatic reprogramming means for countermeasures system.
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Miley Frank P. (Camarillo CA), Counter-countermeasure guidance system.
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Lowenschuss Oscar (Goleta CA), Electronic countermeasure system.
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Reitboeck Heribert J. P. (Pittsburgh PA) Brody Thomas P. (Pittsburgh PA), Identification of radar systems.
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Niemann George W. (Dallas TX), Micro-vector processor.
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Guadagnolo Robert N. (Burbank CA), Pulse repetition interval autocorrelator system.
이 특허를 인용한 특허 (5)
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Williams Steven Scott ; Cook Brett Alan ; Moller Gregory Paul ; Haines Jonathan Williams, Buffer management system for managing the transfer of data into and out of a buffer in a disc drive.
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Williams, Steven Scott; Cook, Brett Alan; Moller, Gregory Paul; Haines, Jonathan Williams, Buffer management system for managing the transfer of data into and out of a buffer in a disc drive.
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Lavoie, Pierre, Hidden Markov modeling for radar electronic warfare.
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Oskouy Rasoul M., Method and apparatus for reporting the status of asynchronous data transfer.
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Shutty John V. ; Kaehler John J. ; Nelson Chris, System for customizing vehicle engine control computer operation.
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