초록 ▼

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are d

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

대표청구항 ▼

A method for handling address translations made by a virtual system (guest) emulated on a multiprocessing (MP) real system having a real main storage and a plurality of real CPUs, guest address translations being put into guest identified entries (guest entries) in a translation lookaside buffer (TL

A method for handling address translations made by a virtual system (guest) emulated on a multiprocessing (MP) real system having a real main storage and a plurality of real CPUs, guest address translations being put into guest identified entries (guest entries) in a translation lookaside buffer (TLB) of any real CPU in the MP real system while the CPU is in emulation state, having a plurality of state descriptor control blocks (SDs) in main storage and each SD representing a virtual CPU and having an SD identifier (SDI) for locating the SD, the MP real system containing one or more virtual systems which may include one or more virtual UP systems (UP guests) and one or more virtual MP systems (MP guests), each UP guest having an associated SD, and each MP guest having a plurality of associated SDs, each SD in main storage being assignable to a virtual MP system or to a virtual UP system, and a CPU identifier (CPU ID) being provided for each real CPU in the MP real system, the method comprising: locating each SD in the real main storage, providing in each SD a last CPU ID field for identifying the last real CPU to use the SD, also providing an SDI register for each real CPU, setting the SDI register of a real CPU to a SDI of a virtual CPU being dispatched upon the real CPU, comparing a previous SDI entered into the SDI register for a real CPU with the SDI of a next guest being dispatched on the real CPU, the next guest being dispatched then becomes the guest on the real CPU, also comparing the content in the last CPU ID field in the SD for the guest being dispatched with the CPU ID for the real CPU upon which the guest is being dispatched, not invalidating any guest TLB entry in the real CPU if the comparing operations find the SDI of the guest being dispatched is equal to the previous SDI in the SDI register, and if the last CPU ID field in the SD of the guest compares equal to the CPU ID of the real CPU, so that the existing guest TLB entries in the CPU are allowed to be used by the guest for a guest program, and invalidating guest TLB entries for the guest being dispatched in the real CPU while in emulation mode if the comparing operations find the last CPU ID field in the SD of the guest being dispatched is not equal to the CPU ID of the real CPU, or if the previous SDI in the SDI register compares unequal with the SDI of the guest being dispatched.