초록 ▼

A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnec

A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

대표청구항 ▼

A multichip integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate, said integrated circuit chips having interconnection pads thereon; a polymer film overlying and bridging said integrated circuit chips, said polymer film having a plura

A multichip integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate, said integrated circuit chips having interconnection pads thereon; a polymer film overlying and bridging said integrated circuit chips, said polymer film having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed on top of said polymer film so as to extend between at least some of said openings and so as to provide electrical connection between at least some of said interconnection pads through said openings.