초록 ▼

A leadless chip carrier for RF power transistors or the like is disclosed which includes a body of insulating material having two major surfaces and side walls joining the major surfaces. In a first embodiment, a pattern of conductive pads is deposited on one major surface. A pattern of conductive c

A leadless chip carrier for RF power transistors or the like is disclosed which includes a body of insulating material having two major surfaces and side walls joining the major surfaces. In a first embodiment, a pattern of conductive pads is deposited on one major surface. A pattern of conductive contact areas is deposited on the other major surface and distributed interconnecting portions of conductive material are deposited to connect the pads to the respective contact areas. In a second embodiment, larger pads and contact areas are provided on a beryllia substrate to provide a leadless chip carrier for RF transistors capable of handling 8 watts. In a third embodiment, a single slot is made conductive to provide the distributed interconnecting portion for one terminal, while in a fourth embodiment, the slot is changed to a plurality of small, tungsten-filled through holes to provide a virtually hermetically sealed leadless chip carrier for RF power transistors.

대표청구항 ▼

A leadless chip carrier suitable for a power semiconductor device having a plurality of terminals, said carrier comprising in combination: a substantially planar substrate of insulating material having two major surfaces and a thickness; a conductive pattern on one of said major surfaces having at l

A leadless chip carrier suitable for a power semiconductor device having a plurality of terminals, said carrier comprising in combination: a substantially planar substrate of insulating material having two major surfaces and a thickness; a conductive pattern on one of said major surfaces having at least a first, second, and third pad for receiving a semiconductive device on one pad thereof; a contact pattern on the other of said major surfaces having at least a first, second, and third area; and distributed interconnecting portions for electrically connecting the first, second, and third pads of the conductive pattern with their associated first, second, and third areas of the contact pattern, whereby said contact pattern permits leadless electrical connection of the chip carrier to accompanying external circuitry, and said distributed interconnecting portions provide wide paths for currents flowing between said conductive pattern and said contact pattern.