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Interboard connection terminal and method of manufacturing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
출원번호 US-0023552 (1987-02-19)
우선권정보 JP-0156621 (1985-07-16); JP-0137961 (1986-06-13)
국제출원번호 PCT/JP86/00364 (1986-07-16)
§371/§102 date 19870219 (19870219)
국제공개번호 WO-8700686 (1987-01-29)
발명자 / 주소
  • Osaki Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Sasaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX)
출원인 / 주소
  • Nippon Telegraph and Telephone Corporation (Chiyoda JPX 03)
인용정보 피인용 횟수 : 60  인용 특허 : 8

초록 ▼

A stack layer structure is formed wherein solderable metal layers are provided at least at two ends thereof, and at least a metal layer for preventing the diffusion of solder is inserted between the two metal layers. In an interboard connection terminal and a method of manufacturing the same, a pair

대표청구항 ▼

An interboard connection terminal comprising: at least one metal layer adapted to prevent diffusion of solder and having two opposed surfaces; a pair of opposed, thin, solderable metal layers stacked one on each of said opposed surfaces of the metal layer; and a pair of solder bumps fused and adhere

이 특허에 인용된 특허 (8)

  1. Mizuno Fukuzo (Fujiyoshida JPX), Ceramic thick film circuit substrate.
    상세보기
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  3. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
    상세보기
  4. Scarlett John A. (Galashiels GB6), Printed circuit boards with solderable plating finishes and method of making the same.
    상세보기
  5. Weitze Artur (Munich DT) Sapunarow Michail (Munich DT), Process for the production of a multi-chip wiring arrangement.
    상세보기
  6. Brown Dale M. (Schenectady NY) Kim Manjin J. (Schenectady NY) Baertsch Richard D. (Scotia NY) Vogelsong Thomas L. (Schenectady NY), Refractory metal capacitor structures, particularly for analog integrated circuit devices.
    상세보기
  7. Marks Robert (South Burlington VT) Phelps ; Jr. Douglas W. (Burlington VT) Ward William C. (Burlington VT), Substrate with multiple type connections.
    상세보기
  8. Reyes Jaime (Birmingham MI) Allred David (Troy MI), Surface mounted circuits including hybrid circuits, having CVD interconnects, and method of preparing the circuits.
    상세보기

이 특허를 인용한 특허 (60)

  1. Swamy Deepak N. (Austin TX), Anisotropic interconnect methodology for cost effective manufacture of high density printed wiring boards.
    상세보기
  2. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  3. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  4. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  5. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Apparatus for locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  6. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
    상세보기
  7. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods.
    상세보기
  8. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers defining lips.
    상세보기
  9. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
    상세보기
  10. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
    상세보기
  11. Robert W. Warren, High density multichip interconnect decal grid array with epoxy interconnects and transfer tape underfill.
    상세보기
  12. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
    상세보기
  13. Brian E. Curcio ; Donald S. Farquhar ; Konstantinos I. Papathomas ; Mark D. Poliks, Method and structure for producing Z-axis interconnection assembly of printed wiring board elements.
    상세보기
  14. Curcio,Brian E.; Farquhar,Donald S.; Papathomas,Konstantinos I.; Poliks,Mark D., Method and structure for producing Z-axis interconnection assembly of printed wiring board elements.
    상세보기
  15. Kaja Suryanarayana ; Prasad Chandrika ; Yu RongQing, Method and structure to prevent distortion and expansion of organic spacer layer for thin film transfer-join technology.
    상세보기
  16. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  17. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux prior to placement.
    상세보기
  18. Potter Curtis N. (Austin TX) Smith Lawrence N. (Austin TX) Kroger Harry (Austin TX), Method of fabricating a high density electrical interconnect.
    상세보기
  19. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Method of forming an assembly board with insulator filled through holes.
    상세보기
  20. Cobbley Chad A. ; Ball Michael B. ; Waddel Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  21. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  22. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  23. Rinne,Glenn A.; Mis,J. Daniel, Methods of forming bumps using barrier layers as etch masks.
    상세보기
  24. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  25. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  26. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
    상세보기
  27. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
    상세보기
  28. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
    상세보기
  29. Fjelstad,Joseph, Methods of making microelectronic packages with conductive elastomeric posts.
    상세보기
  30. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
    상세보기
  31. Altimari Robert J. ; Madden ; Jr. Jean D. ; Maynard Edward R. ; Pitts William E., Multi-tap thin film inductor.
    상세보기
  32. Honda,Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board.
    상세보기
  33. Honda, Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board.
    상세보기
  34. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
    상세보기
  35. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
    상세보기
  36. Matsuda,Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
    상세보기
  37. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
    상세보기
  38. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
    상세보기
  39. Rostoker Michael D. ; Pasch Nicholas F., Optically transmissive preformed planar structures.
    상세보기
  40. Galloway Terry R., Plating process for fine pitch die in wafer form.
    상세보기
  41. Galloway Terry R., Plating process for fine pitch die in wafer form.
    상세보기
  42. Behun John R. (Poughkeepsie NY) Miller William R. (Poughkeepsie NY) Newman Bert H. (Carmel NY) Yankowski Edward L. (Hyde Park NY), Process of fabricating a circuit package.
    상세보기
  43. Ho Chung W ; Wang Tsing-Chow, Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball.
    상세보기
  44. Wen-chou Vincent Wang ; Michael G. Lee ; Solomon Beilin, Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like.
    상세보기
  45. Ogihara Satoru (Hitachi JPX) Numata Shunichi (Hitachi JPX) Miyazaki Kunio (Hitachi JPX) Yokoyama Takashi (Hitachi JPX) Takahashi Ken (Ibaraki JPX) Soga Tasao (Hitachi JPX) Yamada Kazuji (Hitachi JPX), Semiconductor chip module.
    상세보기
  46. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Semiconductor device and assembly board having through-holes filled with filling core.
    상세보기
  47. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Semiconductor device and assembly board having through-holes filled with filling core.
    상세보기
  48. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Semiconductor device and assembly board having through-holes filled with filling core.
    상세보기
  49. Makoto Iijima JP; Tetsushi Wakabayashi JP; Toshio Hamano JP; Masaharu Minamizawa JP; Masashi Takenaka JP; Taturou Yamashita JP; Masataka Mizukoshi JP; Masaru Nukiwa JP; Takao Akai JP, Semiconductor device and method of forming the same.
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  50. Lin, Yen-Liang; Kuo, Tin-Hao; Wu, Sheng-Yu; Chen, Chen-Shien, Semiconductor device having conductive bumps of varying heights.
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  51. Ho, Dong-Ki; Kim, Boseong, Semiconductor package and method of manufacturing the same.
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  52. Danner Paul A. (Beaverton OR), Solder ball array and method of preparation.
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  53. Izuta Goro (Amagasaki JPX) Abe Shunichi (Itami JPX) Nishinaka Yoshirou (Itami JPX) Fukutome Katsuyuki (Itami JPX) Ueda Naoto (Itami JPX) Takeuchi Toshio (Itami JPX) Kashiba Yoshihiro (Amagasaki JPX) , Solder material, junctioning method, junction material, and semiconductor device.
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  54. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
    상세보기
  55. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
    상세보기
  56. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
    상세보기
  57. Rostoker Michael D. ; Pasch Nicholas F., Systems having advanced pre-formed planar structures.
    상세보기
  58. Smith Nicholas J. G. (Cricklade GB2) Ludden Michael J. (Swindon GB2) Nyholm Peter (Swindon GB2) Gibney Paul J. (Swindon GB2), Uses of uniaxially electrically conductive articles.
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  59. Smith Nicholas J. G. (Cricklade GB2) Ludden Michael Joseph (Swindon GB2) Nyholm Peter (Swindon GB2) Gibney Paul James (Swindon GB2), Uses of uniaxially electrically conductive articles.
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  60. Love David George ; Moresco Larry Louis ; Chou William Tai-Hua ; Horine David Albert ; Wong Connie Mak ; Beilin Solomon Isaac, Wire interconnect structures for connecting an integrated circuit to a substrate.
    상세보기

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