초록 ▼

A video signal is time division multiplexed prior to recording using a time base compression device including a random access memory, instead of serial shift registers or the like. Large time base errors in the incoming video signal are accommodated without creating conflicts between memory read and

A video signal is time division multiplexed prior to recording using a time base compression device including a random access memory, instead of serial shift registers or the like. Large time base errors in the incoming video signal are accommodated without creating conflicts between memory read and write operations of successive video lines and without requiring a spare memory. Instead, the time compression random access memory has dual data ports, and successive video lines are loaded into and unloaded out of different locations in the random access memory simultaneously through different ports at different data rates to achieve the requisite time compression. As a result, the usual requirement to route incoming video signals to a spare memory in case of a time base error, for avoiding memory read and write conflicts, is eliminated by the invention.

대표청구항 ▼

A video time division multiplex signal processing system for either multiplexing or demultiplexing a color video signal, said color video signal being characterized by plural color components occurring in plural successive odd and even video lines corresponding to odd and even video line scan period

A video time division multiplex signal processing system for either multiplexing or demultiplexing a color video signal, said color video signal being characterized by plural color components occurring in plural successive odd and even video lines corresponding to odd and even video line scan periods, each of said lines comprising a succession of odd and even video words, said system comprising: (a) memory means having plural memories, each of said memories having a first port and a second port; (b) input/output means, connected to the first port of each of said memories, said input/output means comprising: i. first addressing means for addressing a first set of locations in a first group of said memories during odd ones of said video line scan periods, wherein: said first group of memories comprises as much as one memory for each of said color components, said one memory being adapted to store video data of the corresponding color component, said first set of memory locations corresponding to said odd numbered video lines, ii. second addressing means for addressing a second set of locations in a second group of said memories during even ones of said video line scan periods, wherein: said second group of memories comprises as much as one memory for each of said color components, said one memory being adapted to store video data of the corresponding color component, said second set of memory locations corresponding to said even video lines; (c) output/input means connected to the second port of each of said memories, comprising: i. third addressing means for addressing said first set of memory locations in each of the memories of said first group sequentially in corresponding plural successive intervals during said even video line scan periods at least nearly simultaneously with said second addressing means addressing said second set of memory locations, and ii. fourth addressing means for addressing said second set of memory locations in each of the memories of said second group sequentially in corresponding plural successive intervals during said odd video line scan periods at least nearly simultaneously with said first addressing means addressing said first set of memory locations, wherein said input/output means and said output/input means operate at different data rates for time compression or expansion, whereby said odd and even video lines of each of said components are loaded into different ones of said memories so as to avoid data conflicts between them.