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[미국특허] Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/44
  • H01L-029/52
  • H01L-029/60
출원번호 US-0930162 (1986-11-13)
발명자 / 주소
  • Rothgery Eugene F. (No. Branford CT) Hart William W. C. (Bethany CT) Smith
  • III Edward F. (Madison CT) Phillips Steven D. (Northford CT) Sandel Bonnie B. (Milford CT) Gavin David F. (Cheshire CT)
출원인 / 주소
  • Olin Corporation (New Haven CT 02)
인용정보 피인용 횟수 : 207  인용 특허 : 18

초록 ▼

A package and process of assembling a package adapted for housing an electronic component. The package includes metallic base, lid and leadframe components sealed together with a thermoplastic material. The thermoplastic has an additive consisting essentially of a metal deactivator and a primary ant

대표청구항 ▼

A package adapted for housing an electronic component, comprising: a metallic base component; a metallic lid component; a leadframe disposed between said base component and said lid component; a thermoplastic material sealing said leadframe between said lid and base components; said thermoplastic ma

이 특허에 인용된 특허 (18) 인용/피인용 타임라인 분석

  1. Butt Sheldon H. (Godfrey IL) Smith ; III Edward F. (Madison CT) Gyurina F. Dennis (West Haven CT), Adhesion primers for encapsulating epoxies.
    상세보기
  2. Butt Sheldon H. (Godfrey IL) Smith ; III Edward F. (Madison CT) Gyurina F. Dennis (West Haven CT), Adhesion primers for encapsulating epoxies.
    상세보기
  3. Buchler ; Wilhelm ; Muller ; Gotthard ; Mende ; Hans-Joachim, Arrangement for the sectional cantilever projection of multi-panel bridge supporting structures of steel or prestressed.
    상세보기
  4. Edie Dennis L. (Kobe JA), Bonding rubber to ferrous metal through a deposit of copper and adhesive and laminate therefrom.
    상세보기
  5. Butt Sheldon H. (Godfrey IL), Casing for an electrical component having improved strength and heat transfer characteristics.
    상세보기
  6. Butt Sheldon H. (Godfrey IL) Smith ; III Edward F. (Madison CT) Gyurina F. Dennis (West Haven CT), Casing for electronic components.
    상세보기
  7. Hardy William Baptist (Bound Brook NJ), Copper inhibitors for polyolefins.
    상세보기
  8. Pryor Michael J. (Woodbridge CT), Hybrid and multi-layer circuitry.
    상세보기
  9. Cowell ; George K. ; Cherry ; David J., Metal deactivators as adhesion promotors for vulcanizable elastomers to metals.
    상세보기
  10. Cowell George K. (Brunswick OH NY) Cherry David J. (Somers NY), Metal deactivators as adhesion promotors for vulcanizable elastomers to metals.
    상세보기
  11. Cowell George K. (Medford NJ) Cherry David J. (Grapervine TX), Metal deactivators as adhesion promotors for vulcanizable elastomers to metals.
    상세보기
  12. Butt Sheldon H. (Godfrey IL), Method of making semiconductor casing.
    상세보기
  13. Shearer Wilfred L. (Mountainside NJ) Sinker Stephen M. (Lebanon NJ) Wolf Richard A. (Plainfield NJ), Poly(butylene terephthalate) based molding resins.
    상세보기
  14. Scott Gerald (338 Station Rd. Knowle ; Warwickshire GB2), Process for preparing oxidatively-stable polymers by reaction with antioxidant in the presence of free radical.
    상세보기
  15. Phillips Steven D. (Northford CT) Sandel Bonnie B. (Milford CT), Selected oxyalkylated 2,6-dialkylphenol compounds and their use as stabilizers of organic materials against oxidative de.
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  16. Butt Sheldon H. (Godfrey IL), Semiconductor casing.
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  17. Butt Sheldon H. (Godfrey IL), Semiconductor casing.
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  18. Butt Sheldon H. (Godfrey IL), Semiconductor packages.
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이 특허를 인용한 특허 (207) 인용/피인용 타임라인 분석

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  131. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
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  132. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  133. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  134. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  135. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  136. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
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  137. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  138. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  139. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  140. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  141. Ward William C. (Burlington VT), Semiconductor package.
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  142. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
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  143. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  144. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  145. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  146. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  147. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  148. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  149. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  150. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
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  151. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  152. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  153. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  154. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  155. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
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  156. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
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  157. Paek, Jong Sik, Semiconductor package including flip chip.
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  158. Paek,Jong Sik, Semiconductor package including flip chip.
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  159. Foster, Donald Craig, Semiconductor package including isolated ring structure.
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  160. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
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  161. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
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  162. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.
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  163. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
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  164. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
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  165. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
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  166. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
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  167. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
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  168. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
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  169. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
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  170. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
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  171. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
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  172. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
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  173. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
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  174. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
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  175. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  176. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  177. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
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  178. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
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  179. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
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  180. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
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  181. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
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  182. McCann, David R.; Groover, Richard L.; Hoffman, Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  183. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  184. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  185. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
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  186. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
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  187. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  188. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  189. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  190. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  191. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  192. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  193. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  194. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  195. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
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  196. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
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  197. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
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  198. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  199. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  200. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  201. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  202. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  203. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  204. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  205. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  206. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
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  207. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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