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A bus interface unit for connecting a processor to a memory to form a digital data processing system. The storage locations in the memory are grouped in pages each having a selected access rights mode which regulates access to the data stored therein by the programs, each of which has a selected acc

A bus interface unit for connecting a processor to a memory to form a digital data processing system. The storage locations in the memory are grouped in pages each having a selected access rights mode which regulates access to the data stored therein by the programs, each of which has a selected access rights mode. The access rights are assigned on a page by page basis. If an access request from a program requires transfers to multiple locations, the processor will normally perform an access verification on the first location while it is in the first transfer operation, and then perform the transfer operation and successive transfer operations. If the transfer operations require accesses to separate pages in memory, a microtrap operation is performed and the processor performs access verifications on locations in both pages before performing any transfers.

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In a processor, a bus interface unit for connection to a memory over a bus to form a digital data processing system, said processor including processing means for processing programs each having a selected one of a plurality of access rights modes, said memory including a plurality of addressable st

In a processor, a bus interface unit for connection to a memory over a bus to form a digital data processing system, said processor including processing means for processing programs each having a selected one of a plurality of access rights modes, said memory including a plurality of addressable storage locations each including a like plurality of individually accessible byte locations, the storage locations being group into a plurality of pages each having a selected number of storage locations, with each page having an access right mode, said bus interface unit including: a. transfer means for connection to said processing means and said bus and responsive to a single transfer request from said processing means for initiating a memory access over said bus to two adjacent addressable locations in said memory in two transfers over said bus; b. access verification means connected to said transfer means and responsive to said transfer means initiating a memory access for enabling said transfer means to perform an access verification operation to determine whether the access right mode of said program corresponds to the access right mode of one of the addressable locations; and c. trap means including: i. page test means connected to said transfer means and responsive to said transfer means initiating a memory access to two adjacent locations in memory for determining whether the transfers are to separate pages; ii. page cross verification enabling means connected to said page test means and said access verification means for enabling said access verification means to perform two access verification operations in response to said page test means determining that the transfers are to separate pages, each access verification operation being directed to one of the addressable locations in each of the pages, to determine whether the access mode right of said program corresponds to the access right modes of both of the addressable locations; and iii. page cross transfer enabling means connected to said page test means, said access verification means and said transfer means for disabling said transfer means in response to said page test means determining that the transfers are to separate pages and to thereafter enable said transfer means to engage in the transfers in response to the determination by said access verification means that the access right mode of the program corresponds to the access right modes of both addressable locations whereby regardless of the number of transfer which have to be made to any two pages in response to one transfer request only two access verifications need be made.