초록 ▼

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. I

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality “antialiased”text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the “burst”mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

대표청구항 ▼

A multi-channel pixel data path architecture comprising a plurality of functional elements for communication between a host processor and an all-points addressable frame buffer for use in a video raster display adapter, said data path including; functional element means within said architecture for

A multi-channel pixel data path architecture comprising a plurality of functional elements for communication between a host processor and an all-points addressable frame buffer for use in a video raster display adapter, said data path including; functional element means within said architecture for automatically interconnecting the data path architecture to the frame buffer to selectively provide access to the frame buffer for: (1) operations on a plurality of pixels, (2) operations on a plurality of pixel slices and, (3) operations on bit planes, functional element means within said architecture for selectively performing both logical and arithmetic operations on video data presented to the data path, functional element means within said architecture for extending bit-blt (bit block transfer) operations comprising the parallel access and processing of multiple contiguous pixels of video data from the frame buffer to provide antialiased text and graphics and, functional element means within said architecture for assisting “burst”mode updating of an arbitrary plane of the frame buffer.