초록 ▼

A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle synchronous) processing bus (BUSl through BUSn).

A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle synchronous) processing bus (BUSl through BUSn). Processing can occur on each of the n buses simultaneously. Several processor modules (P boards) are directly coupled to each processing bus, with each P board directly coupled to two buses. Several memory modules (M boards) are directly coupled to each processing bus, with each M board directly coupled to two buses. The functions and architectures of the P boards and M boards are described, along with those of D boards (disk controller modules) and I boards (modules for interfacing the telemetry data processor with its outside environment, which may comprise local area networks, peripherals, gateways, etc.).

대표청구항 ▼

A data processor for high bandwidth data, said data processor having a cylindrical architecture and comprising: means for distributing the data onto n generally parallel buses where n is any preselected positive integer greater than 3; several processor modules directly coupled to each bus, with ea

A data processor for high bandwidth data, said data processor having a cylindrical architecture and comprising: means for distributing the data onto n generally parallel buses where n is any preselected positive integer greater than 3; several processor modules directly coupled to each bus, with each processor module directly coupled to two adjacent buses, where bus(r) is defined as being “adjacent”to bus(r+1) and to bus(r-1), r being any positive integer from 2 through n-1, and, in addition, bus(n) is defined as being “adjacent”to bus(1); and several memory modules directly coupled to each bus, with each memory module directly coupled to two adjacent buses; wherein each individual module has a first, relatively direct, communications relationship with each other module that is directly coupled to a bus to which said individual module is directly coupled in view of the fact that communications between such modules occur over but a single intervening bus, and a second, relatively indirect, communications relationship with each other module that is directly coupled to a bus to which said individual module is not directly coupled in view of the fact that communications between any two such modules is routed via at least one additional intermediate module and two buses; and distinct buses can simultaneously be activated to communicate distinct packets of information between different modules wherein each bus comprises data lines and address lines, and each processor module comprises: first and second ports for coupling to the two adjacent buses, respectively; an address translation/access protection unit coupled to the address lines at each of said ports; a microprocessor coupled to the address translation/access protection unit and to the data lines at each of said ports via a set of transceivers; a first local memory coupled to the address translation/access protection unit and to the data lines at each of said ports; a second local memory coupled directly to the microprocessor and coupled to the address translation/access protection unit via the set of transceivers; and a cache memory coupled directly to the microprocessor, coupled directly to the second local memory, and coupled to the address translation/access protection unit via the set of transceivers.