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Simultaneous multiple level interconnection process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/312
출원번호 US-0262208 (1988-10-19)
발명자 / 주소
  • Flagello Donis G. (Ridgefield CT) Wilczynski Janusz S. (Ossining NY) Witman David F. (Pleasantville NY)
출원인 / 주소
  • International Business Machine Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 60  인용 특허 : 14

초록

A system of establishing a conductive via path between spaced interlevel conductors. Successive layers of metallization separated by a dielectric are built. The vias are opened in one step to eliminate interlevel mashing. The system employs annular pads at locations where contact may be established

대표청구항

A method of establishing a conductive via path between spaced interlevel conductors comprising the steps of: defining a first level having a pattern of a conductive material and applying a first dielectric layer over said first level of conductive material: applying a second level having a pattern o

이 특허에 인용된 특허 (14)

  1. Takayama, Yoshihisa; Gotoh, Kunihiko; Ito, Akihiko; Yamamura, Takeshi; Fujita, Kazuyoshi, Method for fabricating an integrated circuit with multi-layer wiring having opening for fuse.
  2. Alcorn George E. (Fairfax VA) Hamaker Raymond W. (Catharpin VA) Stephens Geoffrey B. (Catlett VA), Method for forming dense dry etched multi-level metallurgy with non-overlapped vias.
  3. Pellegrino Peter P. (216 Edgewood La. Apple Valley MN 55124), Method for mass producing printed circuit boards.
  4. Agnihotri ; Ram Kumar ; Kluge ; II ; Herman Carl, Method of depositing thin films utilizing a polyimide mask.
  5. Tamutus Donald J. (Mercerville NJ), Method of fabricating a color-selection structure for a CRT.
  6. Chang Kenneth (Hopewell Junction NY) Cosman David C. (Newburgh NY) Gartner Helmut M. (Wappingers Falls NY) Hoeg ; Jr. Anthony J. (Wappingers Falls NY), Method of forming thin film interconnection systems.
  7. Birrittella Mark S. (Phoenix AZ) Liaw Hang M. (Scottsdale AZ) Reuss Robert H. (Scottsdale AZ), Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers.
  8. Schachter Herbert I. (86 Campbell St. New Hyde Park ; Long Island NY 11040), Method of making a multi-level circuit board.
  9. Te Velde Ties S. (Eindhoven NLX) Wolters Donald R. (Eindhoven NLX), Method of manufacturing a semiconductor device.
  10. Hulseweh Terry S. (Mesa AZ), Pillar via process.
  11. Takaba Toshio (Tokyo JPX) Kobayashi Toshimasa (Tokyo JPX), Printed wiring board comprising a conductive pattern retreating at least partly in a through-hole.
  12. Balda Raymond J. (Tempe AZ) Bukhman Yefim (Tempe AZ) Goodner Willis R. (Chandler AZ), Process for fabricating semiconductor device.
  13. Johnson Daniel D. (Yorklyn DE) Fritz Herbert L. (Englishtown NJ), Process for forming conductive through-holes through a dielectric layer.
  14. Hazuki Yoshikazu (Tokyo JPX) Moriya Takahiko (Yokosuka JPX), Process for forming multi-layer interconnections.

이 특허를 인용한 특허 (60)

  1. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
  2. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Cleeves, James M., Contact and via structure and method of fabrication.
  6. Ireland, Philip J., Creation of subresolution features via flow characteristics.
  7. Philip J. Ireland, Creation of subresolution features via flow characteristics.
  8. Natzle Wesley Charles, Freestanding multilayer wiring structure.
  9. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for TAB.
  10. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  11. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  12. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  15. Chatterjee Pallab K. (Dallas TX), Integrated circuit with metal interconnecting layers above and below active circuitry.
  16. Chung Henry Wei-Ming (Cupertino CA), Interconnect structures for integrated circuits.
  17. Gardner, Donald S., Interconnection structures and methods of fabrication.
  18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  20. Min Sub Han KR; Tae Gook Lee KR; Wan Soo Kim KR; Byoung Ju Kang KR, Method for forming multi-level metal interconnection.
  21. Teo Yeow Meng,SGX, Method for forming stacked polysilicon.
  22. Bureau, Jean-Marc; Bernard, François, Method for making a sonoprobe.
  23. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  24. Reche John J. (Ventura CA), Method of fabricating hybrid circuit structures.
  25. Nejad, Hasan; Green, James E., Method of fabricating integrated circuitry.
  26. Nejad, Hasan; Green, James E., Method of fabricating integrated circuitry.
  27. Nejad,Hasan; Green,James E., Method of fabricating integrated circuitry.
  28. Olson, Kevin C.; Wang, Alan E., Method of forming solid blind vias through the dielectric coating on high density interconnect (HDI) substrate materials.
  29. Olson, Kevin C.; Wang, Alan E., Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials.
  30. Cleeves, James M., Method of making a contact and via structure.
  31. Fjelstad, Joseph; Haba, Belgacem; Light, David, Method of manufacturing connection components using a plasma patterned mask.
  32. Yates, Donald L., Methods of fabricating integrated circuitry.
  33. Yates,Donald L., Methods of fabricating integrated circuitry.
  34. Park,Cheolsoo, Methods of forming metal lines in semiconductor devices.
  35. Yano Kousaku,JPX ; Ueda Tetsuya,JPX, Multi-layer wiring structure having varying-sized cutouts.
  36. Sasaki, Keiichi; Kimura, Manabu; Hisatsune, Yoshimi; Hayasaka, Nobuo, Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method.
  37. Sasaki,Keiichi; Kimura,Manabu; Hisatsune,Yoshimi; Hayasaka,Nobuo, Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method.
  38. Philip J. Ireland, Process for forming electrical interconnects in integrated circuits.
  39. Nathan Richard J. ; Lan James J. D. ; Chiang Steve S., Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect.
  40. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  41. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  42. Yano Kousaku,JPX ; Ueda Tetauya,JPX, Semiconductor device and its manufacturing method.
  43. Kikuchi, Hirokazu, Semiconductor device with interconnection connecting to a via.
  44. Ikemasu, Shinichiroh; Okawa, Narumi, Semiconductor memory device having electrical connection by side contact.
  45. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  46. Ema, Taiji; Anezaki, Tohru, Semiconductor storage device and method for fabricating the same.
  47. Bronner Gary B. ; Costrini Greg ; Radens Carl J. ; Schnabel Rainer F., Slotted damascene lines for low resistive wiring lines for integrated circuit.
  48. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  49. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  50. Ireland, Philip J., Subresolution features for a semiconductor device.
  51. Ireland, Philip J., Subresolution features for a semiconductor device.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. McMahon, James; Smith, Ryan S.; LiCausi, Nicholas V.; Ryan, Errol Todd; Zhang, Xunyuan; Law, Shao Beng, Via and skip via structures.
  60. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.
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