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Non-volatile electronic memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-011/22
출원번호 US-0007048 (1987-01-27)
우선권정보 DE-3602887 (1986-01-31)
발명자 / 주소
  • Pott Richard (Leverkusen DEX) Eiling Aloys (Bochum DEX) Kmpf Gnther (Krefeld DEX)
출원인 / 주소
  • Bayer Aktiengesellschaft (Leverkusen DEX 03)
인용정보 피인용 횟수 : 67  인용 특허 : 4

초록

A volatile semiconductor memory module (RAM) is combined with a permanent memory based on an electrically polarizable, preferably ferroelectric, layer within an integrated monolithic module in such a manner that, as a result of a STORE command, the information present in the semiconductor memory is

대표청구항

A non-volatile integrated electronic memory module comprising a volatile semiconductor memory module (RAM) region and a permanent memory electrically polarisable ferroelectric layer region within an integrated monolithic module and means to retrieve and transfer information from said ferroelectric l

이 특허에 인용된 특허 (4)

  1. Geary John M. (Summit NJ), Ferroelectric digital device.
  2. Cook Robert C. (Palo Alto CA), Monolithic semiconductor integrated circuit ferroelectric memory device.
  3. Rohrer George A. (Benton Harbor MI) McMillan Larry (Longmont CO), Monolithic semiconductor integrated circuit ferroelectric memory device, and methods of fabricating and utilizing same.
  4. Cook Robert C. (Palo Alto CA), Monolithic semiconductor integrated circuit-ferroelectric memory drive.

이 특허를 인용한 특허 (67)

  1. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Addressable and electrically reversible memory switch.
  2. Evans Thomas A. ; Argos ; Jr. George, Completely encapsulated top electrode of a ferroelectric capacitor.
  3. Eastep Brian Lee ; Evans Thomas A., Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer.
  4. Eastep Brian Lee ; Evans Thomas A., Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced escapsulation layer.
  5. Argos George ; Yamazaki Tatsuya,JPX, Dual-level metalization method for integrated circuit ferroelectric devices.
  6. Zelner, Marina; Capanu, Mircea; Woo, Paul Bun Cheuk; Nagy, Susan C., Electronic component with reactive barrier and hermetic passivation layer.
  7. Zelner, Marina; Capanu, Mircea; Woo, Paul Bun Cheuk; Nagy, Susan C., Electronic component with reactive barrier and hermetic passivation layer.
  8. Zelner, Marina; Woo, Paul Bun Cheuk; Capanu, Mircea; Nagy, Susan C.; Cervin, Andrew Vladimir Claude, Electronic component with reactive barrier and hermetic passivation layer.
  9. Miller William D. (Rio Rancho NM) Evans Joseph T. (Albuquerque NM) Kinney Wayne I. (Albuquerque NM) Shepherd William H. (Corrales NM), Fabrication of ferroelectric capacitor and memory cell.
  10. Evans Thomas A., Ferroelectric memory device structure useful for preventing hydrogen line degradation.
  11. Thomas A. Evans, Ferroelectric memory device structure useful for preventing hydrogen line degradation.
  12. Evans ; Jr. Joseph T. ; Bullington Jeff A. ; Bernacki Stephen E. ; Armstrong Bruce G., Ferroelectric memory structure.
  13. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  14. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  15. Dimmler,Klaus; Gnadinger,Alfred P., Ferroelectric transistor for storing two data bits.
  16. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor with enhanced data retention.
  17. Mandell, Aaron; Perlman, Andrew, Floating gate memory device using composite molecular material.
  18. Bailey, Richard A., HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCU.
  19. Bailey Richard A., Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circu.
  20. Whitaker, Mark R.; Marentette, Leslie Joseph, Interrupt generation and acknowledgment for RFID.
  21. Whitaker, Mark R., Low power, low pin count interface for an RFID transponder.
  22. Gallagher William Joseph (Ardsley NY) Kaufman James Harvey (San Jose CA) Parkin Stuart Stephen Papworth (San Jose CA) Scheuerlein Roy Edwin (Cupertino CA), Magnetic memory array using magnetic tunnel junction devices in the memory cells.
  23. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  24. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  25. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  26. Krieger, Juri H.; Yudanoy, Nikolai, Memory device.
  27. Moriya, Yoshitaka; Watanabe, Yasuko; Arai, Yasuyuki, Memory device and semiconductor device.
  28. Moriya, Yoshitaka; Watanabe, Yasuko; Arai, Yasuyuki, Memory device and semiconductor device.
  29. Krieger, Juri H.; Yudanov, N. F., Memory device with a self-assembled polymer film and method of making the same.
  30. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active and passive layers.
  31. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
  32. Seyyedy Mirmajid, Method for making three dimensional ferroelectric memory.
  33. Asakawa, Tsutomu, Method for manufacturing non-volatile memory device and non-volatile memory and semiconductor device.
  34. Asakawa, Tsutomu, Method for manufacturing non-volatile memory device and non-volatile memory device and semiconductor device.
  35. Evans, Jr., Joseph T.; Miller, William D.; Womack, Richard H., Method for reading non-volatile ferroelectric capacitor memory cell.
  36. Evans Thomas A. ; Argos ; Jr. George, Method of fabricating partially or completely encapsulated top electrode of a ferroelectric capacitor.
  37. Gnadinger Alfred P. (Colorado Springs CO), Method of making a ferroelectric capacitor and forming local interconnect.
  38. Hartner, Walter; Schindler, G?nther; Weinrich, Volker; Kasko, Igor, Method of manufacturing a ferroelectric capacitor configuration.
  39. Evans Thomas A., Method of manufacturing ferroelectric memory device useful for preventing hydrogen line degradation.
  40. Krieger, Juri H.; Yudanov, Nikolay F., Molecular memory cell.
  41. Krieger,Juri H; Yudanov,Nicolay F, Molecular memory cell.
  42. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Molecular memory device.
  43. Evans, Jr., Joseph T.; Miller, William D.; Womack, Richard H., Non-volatile memory circuit using ferroelectric capacitor storage element.
  44. Evans, Jr., Joseph T.; Miller, William D.; Womack, Richard H., Non-volatile memory circuit using ferroelectric capacitor storage element.
  45. Redecker, Michael, Non-volatile memory device and matrix display panel using the same.
  46. Kingsborough,Richard P.; Sokolik,Igor, Organic thin film Zener diodes.
  47. Evans Thomas A. ; Argos ; Jr. George, Partially or completely encapsulated top electrode of a ferroelectric capacitor.
  48. Evans Thomas A. ; Argos ; Jr. George, Partially or completely encapsulated top electrode of a ferroelectric capacitor.
  49. Argos ; Jr. George (Colorado Springs CO) Spano John D. (Colorado Springs CO) Traynor Steven D. (Colorado Springs CO), Passivation method and structure using hard ceramic materials or the like.
  50. Hsu Louis Lu-Chen ; Mandelman Jack Allan ; Assaderaghi Fariborz, Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure.
  51. Whitaker, Mark R.; Greefkes, Kirk, RFID interface and interrupt.
  52. Scheuerlein Roy Edwin, Read circuit for magnetic memory array using magnetic tunnel junction devices.
  53. Moazzami Reza (Oakland CA) Jaffe James M. (Santa Clara CA), Refreshing ferroelectric capacitors.
  54. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Reversible field-programmable electric interconnects.
  55. Bulovic,Vladimir; Mandell,Aaron; Perlman,Andrew, Reversible field-programmable electric interconnects.
  56. Cheung, Patrick K.; Khathuria, Ashok M., Self aligned memory element and wordline.
  57. Cheung,Patrick K.; Khathuria,Ashok M., Self aligned memory element and wordline.
  58. Saito, Toshihiko, Semiconductor device and manufacturing method thereof.
  59. Saito, Toshihiko, Semiconductor device and manufacturing method thereof.
  60. Saito, Toshihiko, Semiconductor device and manufacturing method thereof.
  61. Moriya, Yoshitaka; Abe, Hiroko; Yukawa, Mikio; Nomura, Ryoji, Semiconductor device and method for manufacturing the same.
  62. Akao Yasushi,JPX ; Kuroda Kenichi,JPX, Semiconductor integrated circuit device.
  63. Akao Yasushi,JPX ; Kuroda Kenichi,JPX, Semiconductor integrated circuit device.
  64. Yasushi Akao JP; Kenichi Kuroda JP, Semiconductor integrated circuit device.
  65. Gnadinger, Alfred P., Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric.
  66. Gnadinger,Fred P., Single transistor rare earth manganite ferroelectric nonvolatile memory cell.
  67. Seyyedy Mirmajid, Three dimensional ferroelectric memory.
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