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A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all se

A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all segments using only adders and registers. The convolution products are then summed in a pipeline adder tree to derive the convolution of the complete input word. This architecture provides high frequency capability and significantly lower transistor count and hardware complexity, enabling efficient very large scale integration (VLSI) implementation.

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A multiplierless digital transversal filter comprising: a first set of N registers for respectfully receiving and storing respective coefficients of a set of N filter tap coefficients Ci, where i=0, 1, . . . N-1, each coefficient having L bits in successive bit positions j, where j=0, 1, . . . , L-1

A multiplierless digital transversal filter comprising: a first set of N registers for respectfully receiving and storing respective coefficients of a set of N filter tap coefficients Ci, where i=0, 1, . . . N-1, each coefficient having L bits in successive bit positions j, where j=0, 1, . . . , L-1; means for receiving successive samples xn of a digital input word X, all bits of a sample xn being received in parallel and each such sample having M bits in successive bit positions k, where k=0, 1, . . . , M-1; means to bit slice each input word sample xn into a plurality of segments, each segment having a number w of bits, each segment constituting a processing plane of said filter; means to perform a convolution of the w-bits of the bit-slice segment of each of said processing planes by said set of coefficients Ci in parallel, each segment being convolved with said set of coefficients Ci, the output of each processing plane being the convolution of the w-bits of the bit slice segment thereof and the L bits of each of said set of coefficients Ci; means to add the results of all said convolutions of all of said M bits of each input word sample xn, the sum so derived being Yn; means to output said sum Yn as a filtered digital output signal sample corresponding to said input word sample xn; and means for biasing the input word samples xn and the coefficients Ci so that they represent only positive numbers, whereby said sum Yn is derived over all four possible quadrants of the results of each of said convolutions.