초록 ▼

A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific s

A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.

대표청구항 ▼

A digital signal processing apparatus comprising: a host processor having a data bus and an address bus; first and second dual port memory elements, wherein each of said memory elements has first and second data and address interfaces, said first data interfaces of said first and second memory eleme

A digital signal processing apparatus comprising: a host processor having a data bus and an address bus; first and second dual port memory elements, wherein each of said memory elements has first and second data and address interfaces, said first data interfaces of said first and second memory elements being coupled to said host processor data bus, and said first address interfaces of said first and second memory elements being coupled to said host processor address bus; and first and second coprocessors each being for performing predetermined arithmetic functions required by digital signal processing applications, and each having a data bus and a data address bus, said first coprocessor data bus being coupled to said first memory element second data interface, said first coprocessor data address bus being coupled to said first memory element second address interface, said second coprocessor data bus being coupled to said second memory element second data interface, and said second coprocessor data address bus being coupled to said second memory element second address interface.