초록 ▼

Decoupling capacitance is provided with negligible inductance in a high speed discrete wire logic panel by the use of SMT (surface mounting) capacitors that are mounted in holes in the circuit board. A hole is formed in the circuit board under each location where a dual-in-line IC (integrated circui

Decoupling capacitance is provided with negligible inductance in a high speed discrete wire logic panel by the use of SMT (surface mounting) capacitors that are mounted in holes in the circuit board. A hole is formed in the circuit board under each location where a dual-in-line IC (integrated circuit) is to be mounted, and an SMT capacitor is mounted in the hole, with the opposite terminals of the capacitor soldered to the conductive layers on opposite board surfaces. Each quantity of solder extends substantially in the plane of a corresponding conductive layer. Only one side of each capacitor terminal is soldered to a conductive layer, to permit flux washout. In the PGA (pin grid array) area of the circuit board, a capacitor is selectively mounted under an IC by removing a pin from a hole lying under the pin-free area in the center of the IC, and installing a capacitor in the hole.

대표청구항 ▼

A high speed logic panel comprising: a board member of insulative material having upper and lower faces; voltage and ground conductive layers, each lying on and covering a majority of one of said board member faces and forming conductive planes on corresponding board faces; said board member and con

A high speed logic panel comprising: a board member of insulative material having upper and lower faces; voltage and ground conductive layers, each lying on and covering a majority of one of said board member faces and forming conductive planes on corresponding board faces; said board member and conductive planes having a multiplicity of aligned capacitor-receiving through holes; a multiplicity of elongated leadless decoupling capacitors each having an elongated body with a middle and opposite ends and whose outside is insulative at said middle and which has electrically conductive layers at said ends forming capacitor terminals, each capacitor having a capacitance between said terminals, each capacitor lying in one of said holes with said terminals lying respectively adjacent to said voltage and ground conductive layers; a quantity of solder extending between each capacitor terminal and an adjacent portion of a corresponding one of said conductive planes; each capacitor includes two groups of interfitting conductive films extending in cross planes perpendicular to said conductive planes and merging with said terminals, and each quantity of solder forms a conductive path extending between a capacitor terminal and a conductive plane lying primarily in a corresponding one of said conductive planes.