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[미국특허] Sealing and stress relief layers and use thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-003/00
  • B32B-007/00
  • B44C-001/22
  • B29C-037/00
출원번호 US-0167290 (1988-03-11)
발명자 / 주소
  • Boss David W. (Beacon NY) Carr Timothy W. (Hopewell Junction NY) Dubetsky Derry J. (Wappingers Falls NY) Greenstein George M. (Hopewell Junction NY) Grobman Warren D. (Carmel NY) Hayunga Carl P. (Pou
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 34  인용 특허 : 8

초록 ▼

Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin

대표청구항 ▼

A structure for electrically interconnecting a substrate having conductive vias therein and associated articles comprising: at least one first conductive bonding pad disposed on the surface of said substrate in alignment with said conductive vias; at least one layer of polymeric material disposed on

이 특허에 인용된 특허 (8) 인용/피인용 타임라인 분석

  1. Schaible Paul M. (Poughkeepsie NY) Suierveld John (San Jose CA), Method for forming conductive lines and vias.
    상세보기
  2. Magdo Ingrid E. (Hopewell Junction NY) Ormond ; Jr. Douglas W. (Wappingers Falls NY), Method for producing a plurality of layers of metallurgy.
    상세보기
  3. Ito ; Satoru ; Ota ; Masataka ; Sugawara ; Katsuro, Method of forming passivation film.
    상세보기
  4. Niwa Koichi (Tama JPX) Murase Teruo (Tokorozawa JPX) Fujimori Masatoshi (Musashino JPX) Murakawa Kyohei (Yokohama JPX), Method of manufacturing multilayer ceramic board.
    상세보기
  5. Watanabe Yutaka (Hadano JPX) Kobayashi Fumiyuki (Sagamihara JPX) Ogihara Satoru (Hitachi JPX) Ohzawa Yoshiyuki (Hiratsuka JPX), Multi-layer ceramic substrate and method for the production thereof.
    상세보기
  6. Nakakita Shoji (Tokyo JPX), Multi-layered substrate having a fine wiring structure for LSI or VLSI circuits.
    상세보기
  7. Desai Kamalesh S. (Wappingers Falls NY), Multilayer ceramic substrate and process for forming therefor.
    상세보기
  8. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
    상세보기

이 특허를 인용한 특허 (34) 인용/피인용 타임라인 분석

  1. Sherrer, David W.; Rollin, Jean-Marc, Batch fabricated microconnectors.
    상세보기
  2. Sherrer, David W.; Rollin, Jean-Marc, Batch fabricated microconnectors.
    상세보기
  3. Fasano Benjamin V. ; Indyk Richard F. ; Kamath Sundar M. ; Knickerbocker John U. ; Langenthal Scott I. ; O'Connor Daniel P. ; Reddy Srinivasa S. N., Ceramic substrate having a sealed layer.
    상세보기
  4. Sherrer, David, Coaxial transmission line microstructure with a portion of increased transverse dimension and method of formation thereof.
    상세보기
  5. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructure having center and outer conductors configured in a rectangular cross-section.
    상세보기
  6. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructures having an active device and methods of formation thereof.
    상세보기
  7. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructures having conductors formed by plural conductive layers.
    상세보기
  8. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive connecting pin for package substance.
    상세보기
  9. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive connecting pins for a package substrate.
    상세보기
  10. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive pin attached to package substrate.
    상세보기
  11. Hiramatsu,Yasuji; Ito,Yasutaka, Device used to produce or examine semiconductors.
    상세보기
  12. Sherrer, David W.; Reid, James R., Devices and methods for solder flow control in three-dimensional microstructures.
    상세보기
  13. Sherrer, David W.; Reid, Jr., James R., Devices and methods for solder flow control in three-dimensional microstructures.
    상세보기
  14. Brunner, Sebastian; Feichtinger, Thomas; Pudmich, Günter; Schlick, Horst; Schmidt-Winkel, Patrick, Electric component and component and method for the production thereof.
    상세보기
  15. Rollin, Jean-Marc; Sherrer, David W., Integrated electronic components and methods of formation thereof.
    상세보기
  16. Rollin, Jean-Marc; Sherrer, David W., Integrated electronic components and methods of formation thereof.
    상세보기
  17. Sachdev Krishna Gandhi ; Hummel John Patrick ; Kamath Sundar Mangalore ; Lang Robert Neal ; Nendaic Anton ; Perry Charles Hampton ; Sachdev Harbans, Low TCE polyimides as improved insulator in multilayer interconnect structures.
    상세보기
  18. Frech Roland,DEX ; Garben Bernd,DEX ; Harrer Hubert,DEX ; Klink Erich,DEX, Mesh planes for multilayer module.
    상세보기
  19. Schofield Kevin H., Method of laser ablation of semiconductor structures.
    상세보기
  20. Sherrer, David W.; Cardwell, Dara L., Methods of fabricating electronic and mechanical structures.
    상세보기
  21. Rollin, Jean-Marc; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken; Oliver, J. Marcus; Smith, Tim, Microstructure including microstructural waveguide elements and/or IC chips that are mechanically interconnected to each other.
    상세보기
  22. Reid, James Robert, Multi-layer digital elliptic filter and method.
    상세보기
  23. Reid, James Robert, Multi-layer digital elliptic filter and method.
    상세보기
  24. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Package substrate with a conductive connecting pin.
    상세보기
  25. Dyer,Thomas W.; Fang,Sunfei; Yan,Jiang, Self-aligned dual segment liner and method of manufacturing the same.
    상세보기
  26. Rollin, Jean-Marc; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken; Oliver, J. Marcus; Smith, Tim, Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    상세보기
  27. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free interconnected electronic mechanical structural systems.
    상세보기
  28. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free interconnected electronic mechanical structural systems.
    상세보기
  29. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free mechanical interconnection of electronic sub-systems using a spring configuration.
    상세보기
  30. Vanhille, Kenneth; Sherrer, David, Thermal management.
    상세보기
  31. Houck, William D.; Sherrer, David W., Three-dimensional microstructure having a first dielectric element and a second multi-layer metal element configured to define a non-solid volume.
    상세보기
  32. Houck, William D.; Sherrer, David W., Three-dimensional microstructures having a re-entrant shape aperture and methods of formation.
    상세보기
  33. Sherrer, David, Transition structure between a rectangular coaxial microstructure and a cylindrical coaxial cable using step changes in center conductors thereof.
    상세보기
  34. Vanhille, Kenneth; Sherrer, David, Waveguide balun having waveguide structures disposed over a ground plane and having probes located in channels.
    상세보기

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