초록 ▼

A power-on reset circuit includes a start-up voltage generator circuit which produces a voltage which is insensitive to changes in the threshold voltages of the field effect transistors contained therein. The start-up voltage then controls a trigger voltage for sheering a current to a capacitor, the

A power-on reset circuit includes a start-up voltage generator circuit which produces a voltage which is insensitive to changes in the threshold voltages of the field effect transistors contained therein. The start-up voltage then controls a trigger voltage for sheering a current to a capacitor, the current being provided by a switchable current source. The capacitor charges, therein introducing a delay into the generation of the reset signal. The reset signal is fedback to the start-up voltage generator circuit to reduce the steady state current drawn by the power-on reset circuit. A test terminal is provided to force the reset signal to go low for in circuit testing. This also provides a means for resetting internal memory elements which may be couple to the output of the power-on reset circuit to a known state.

대표청구항 ▼

An MOS power-on reset circuit having at least one threshold voltage for generating a reset signal when a first supply voltage is applied to said power-on reset circuit, comprising; first means coupled to the first supply voltage for generating a start-up voltage wherein the start-up voltage is subst

An MOS power-on reset circuit having at least one threshold voltage for generating a reset signal when a first supply voltage is applied to said power-on reset circuit, comprising; first means coupled to the first supply voltage for generating a start-up voltage wherein the start-up voltage is substantially unaffected by variations in said at least one threshold voltage; second means coupled to said first means for generating a trigger voltage in response to the start-up voltage; a current source coupled to the first supply voltage; a first capacitor coupled between said current source and a second supply voltage; third means coupled to said current source and to said second means and responsive to the trigger voltage for steering a current from said current source to said first capacitor; and a driver means coupled to said first capacitor for producing the reset signal and further coupled to said first means for reducing the steady state current to substantially zero.