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A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N×N dots. The circuit includes first and second memory units each including a plurality of words formed i

A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N×N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N×N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N×N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.

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A vector pattern processing circuit for a bit map display system including a display unit having a plurality of memory regions in matrix form defined in a plane of said display unit, each memory region forming N×N dots, comprising: first and second memory means arranged in parallel for storing a plu

A vector pattern processing circuit for a bit map display system including a display unit having a plurality of memory regions in matrix form defined in a plane of said display unit, each memory region forming N×N dots, comprising: first and second memory means arranged in parallel for storing a plurality of words formed in a matrix, each word having an N×N bits structure, said words in said first memory means corresponding to dot data of a first group of diagonally arranged memory regions of said display unit and said words in said second memory means corresponding to dot data of a second group of diagonally arranged memory regions of said display unit; first word register means, operatively connected to said first memory means, for storing dot data of said first diagonally arranged memory region group; second word register means operatively connected to said second memory means for storing dot data of said second diagonally arranged memory region group; vector pattern generation circuit means for receiving start and end coordinates in said diagonally arranged memory regions defining a processing vector pattern, for generating vector pattern dot data arranged in a plane defined by a horizontal axis and a vertical axis perpendicular to said primary axis in response to a gradient of said vector pattern, and for generating control signals for selecting one word from each other of said first and second memory means in accordance with said gradients of said vector pattern; bit setting circuit means, operatively connected between said first and second word register means and said vector pattern generation circuit means, for energizing one of said first and second word register means in response to said pattern dot data from said vector pattern generation circuit means, and for setting a bit to said energized word register means in each dot data generation time at said vector pattern generation circuit means, so that each of said pattern dot data is set in the corresponding word register means for storing dot data of the corresponding diagonally arranged memory unit; and store control circuit means, operatively connected to said first and second memory means and said vector pattern generation circuit means, for receiving said start coordinate and addressing at least one address of a word in one of said memory means defined by said start coordinate and said control signals, so that at least one data set stored in one of said word register means is stored in said word of the corresponding memory means defined by said address.