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Method of manufacturing an interboard connection terminal 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
출원번호 US-0173745 (1988-03-25)
우선권정보 JP-0156621 (1985-07-16); JP-0137961 (1986-06-13)
발명자 / 주소
  • Osaka Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Susaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX)
출원인 / 주소
  • Nippon Telegraph and Telephone (Tokyo JPX 03)
인용정보 피인용 횟수 : 71  인용 특허 : 8

초록

A stack layer structure is formed wherein solderable metal layers are provided at least at two ends thereof, and at least a metal layer for preventing the diffusion of solder is inserted between the two metal layers. In an interboard connection terminal and a method of manufacturing the same, a pair

대표청구항

A method of manufacturing an interboard connection terminal, comprising the steps of: forming a metal interlayer of a three-layer structure by forming a through-hole in an unsolderable and insulating support board, forming a first metal layer by charging a solderable metal located into part of the t

이 특허에 인용된 특허 (8)

  1. Mizuno Fukuzo (Fujiyoshida JPX), Ceramic thick film circuit substrate.
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  3. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
  4. Scarlett John A. (Galashiels GB6), Printed circuit boards with solderable plating finishes and method of making the same.
  5. Weitze Artur (Munich DT) Sapunarow Michail (Munich DT), Process for the production of a multi-chip wiring arrangement.
  6. Brown Dale M. (Schenectady NY) Kim Manjin J. (Schenectady NY) Baertsch Richard D. (Scotia NY) Vogelsong Thomas L. (Schenectady NY), Refractory metal capacitor structures, particularly for analog integrated circuit devices.
  7. Marks Robert (South Burlington VT) Phelps ; Jr. Douglas W. (Burlington VT) Ward William C. (Burlington VT), Substrate with multiple type connections.
  8. Reyes Jaime (Birmingham MI) Allred David (Troy MI), Surface mounted circuits including hybrid circuits, having CVD interconnects, and method of preparing the circuits.

이 특허를 인용한 특허 (71)

  1. Wong Stephen H. P.,CAX ; Kiang Billy,CAX, Apparatus and method for connecting printed circuit boards through soldered lap joints.
  2. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
  3. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
  4. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
  5. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Apparatus for locating conductive spheres utilizing screen and hopper of solder balls.
  6. Kang,Teck Gyu; Kubota,Yoichi, Assemblies having stacked semiconductor chips and methods of making same.
  7. Johnson, Kenneth William, Back side probing method and assembly.
  8. Park Sang Wook,KRX ; Kim Ji Yon,KRX, Chip size package and method of fabricating the same.
  9. Yoshizawa Tetsuo,JPX ; Nishida Hideyuki,JPX ; Imaizumi Masaaki,JPX ; Ichida Yasuteru,JPX ; Konishi Masaki,JPX ; Kondo Hiroshi,JPX ; Sakaki Takashi,JPX, Circuit member and electric circuit device with the connecting member.
  10. Kim,Young Gon; Gibson,David; Warner,Michael; Damberg,Philip; Osborn,Philip, Components, methods and assemblies for multi-chip packages.
  11. Yamasaki Kozo,JPX ; Saiki Hajime,JPX, Connecting board.
  12. Sakai Tadahiko,JPX ; Sakemi Shoji,JPX, Electronic device mounting method.
  13. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
  14. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods.
  15. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers defining lips.
  16. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
  17. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
  18. Himmel Richard P. (Mission Viejo CA) Brown Raymond (Fountain Valley CA), Green ceramic via metallization technique.
  19. Lemke, Timothy A.; Houtz, Timothy W., High density connector and method of manufacture.
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  21. Badehi, Avner, Integrated circuit device.
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  24. Murphy James V., Integrated circuit intercoupling component with heat sink.
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  26. Nelson Bradley H. (Austin TX), Method of assembling stacks of integrated circuit dies.
  27. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
  28. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux prior to placement.
  29. Cobbley Chad A. ; Ball Michael B. ; Waddel Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
  30. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
  31. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
  32. Rinne,Glenn A.; Mis,J. Daniel, Methods of forming bumps using barrier layers as etch masks.
  33. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
  34. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
  35. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
  36. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
  37. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
  38. Fjelstad,Joseph, Methods of making microelectronic packages with conductive elastomeric posts.
  39. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
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  41. Bang,Kyong Mo; Kang,Teck Gyu; Park,Jae M., Microelectronic packages with self-aligning features.
  42. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
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  44. Matsuda,Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
  45. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
  46. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
  47. Galloway Terry R., Plating process for fine pitch die in wafer form.
  48. Galloway Terry R., Plating process for fine pitch die in wafer form.
  49. Nishiyama Tousaku,JPX, Printed wiring board and assembly of the same.
  50. Wen-chou Vincent Wang ; Michael G. Lee ; Solomon Beilin, Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like.
  51. Lee, Jin Hyuk, Semiconductor device and manufacturing method using a stress-relieving film attached to solder joints.
  52. Hashimoto,Nobuaki, Semiconductor device and method for manufacture thereof, circuit board, and electronic instrument.
  53. Hashimoto,Nobuaki, Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument.
  54. Lin, Yen-Liang; Kuo, Tin-Hao; Wu, Sheng-Yu; Chen, Chen-Shien, Semiconductor device having conductive bumps of varying heights.
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  56. Hashimoto, Nobuaki, Semiconductor device with a plurality of stacked boards and method of making.
  57. Ho, Dong-Ki; Kim, Boseong, Semiconductor package and method of manufacturing the same.
  58. Danner Paul A. (Beaverton OR), Solder ball array and method of preparation.
  59. Murphy James V., Solder ball terminal.
  60. Murphy James V., Solder ball terminal.
  61. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
  62. Wilson, Stuart E.; Green, Ronald; Crisp, Richard Dewitt; Humpston, Giles, Stack microelectronic assemblies.
  63. Spielberger, Richard K.; Jensen, Ronald J.; Wagner, Thomas G., Stacked ball grid array.
  64. Yabuki,Richard; Tea,Nim, Stacked contact bump.
  65. Haba, Belgacem, Stacked microelectronic assemblies with central contacts.
  66. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.
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  68. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S.; Zohni, Wael; Mohammed, Ilyas, Stacked packages.
  69. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
  70. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
  71. Zhang, Leilei; Bokharey, Zuhair, Variable-size solder bump structures for integrated circuit packaging.
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