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[미국특허] Sloped contact etch process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B44C-001/22
  • C03C-015/00
  • C03C-025/06
  • B29C-037/00
출원번호 US-0355574 (1989-05-23)
발명자 / 주소
  • Berglund Robert K. (Mesa AZ) Mautz Karl E. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 57  인용 특허 : 4

초록

A method for etching vias having sloped sidewalls is provided, wherein the vias are formed in an interlayer dielectric formed on top of an interconnect layer using a patterned photoresist film as a mask. A top portion of the via is formed with a wet etch process which isotropically undercuts the mas

대표청구항

A method for making electrical contact between a first conductive layer and a second conductive layer of a semiconductor device wherein an insulating layer separates the first conductive layer and the second conductive layer, the method comprising the steps of: forming a masking film with a predeter

이 특허에 인용된 특허 (4)

  1. Nemiroff Michael H. (Del Mar CA), Method of fabricating a tapered via hole in polyimide.
  2. Sugishima Kenji (Kawasaki JPX) Takada Tadakazu (Kawasaki JPX), Method of manufacturing a semiconductor device.
  3. Diem Bernard (Meylan FRX), Process for producing by sloping etching a thin film transistor with a self-aligned gate with respect to the drain and s.
  4. Berglund Robert K. (Mesa AZ) Mautz Karl E. (Chandler AZ) Tyldesley Roger (Mesa AZ), Sloped contact etch process.

이 특허를 인용한 특허 (57)

  1. Lu, David; Tseng, Horng-Huei; Jang, Syun-Ming, Anchored damascene structures.
  2. Gonzalez, Fernando; Sandhu, Gurtej S.; Violette, Mike P., Conductors in semiconductor devices.
  3. Andricacos,Panayotis; Cooper,Emanuel Israel; Dalton,Timothy Joseph; Deligianni,Hariklia; Guidotti,Daniel; Kwietniak,Keith Thomas; Steen,Michelle Leigh; Tsang,Cornelia Kang I, Deep filled vias.
  4. Licata Thomas John ; Nunes Ronald Wayne ; Okazaki Motoya, Dual damascene process having tapered vias.
  5. Rodgers T. J. ; Geha Sam ; Petti Chris ; Yen Ting-Pwu, Edge metal for interconnect layers.
  6. Wodecki, Norman, Etching method for preparing a stepped structure.
  7. Hwang Jeng H. ; Ying Chentsau ; Chiang Kang-Lie ; Mak Steve S. Y., Etching methods for anisotropic platinum profile.
  8. Jeng H. Hwang, Etching methods for anisotropic platinum profile.
  9. Ghosh, Amalkumar P.; Vazan, Fridrich; Anandan, Munisamy; Donoghue, Evan; Khayrullin, Ilyas I.; Ali, Tariq; Tice, Kerry, High-precision shadow-mask-deposition system and method therefor.
  10. Hwang Jeng H. ; Ying Chentsau ; Jin Guang Xiang ; Mak Steve S. Y., Iridium etchant methods for anisotropic profile.
  11. Hwang, Jeng H.; Mak, Steve S. Y.; Lin, True-Lon; Ying, Chentsau; Schaller, John W., Masking methods and etching sequences for patterning electrodes of high density RAM capacitors.
  12. Yu, Lianzhong; Ried, Robert P.; Goldberg, Howard D.; Yu, Duli, Merged-mask micro-machining process.
  13. Hasegawa Kiyoshi,JPX ; Ozaki Hiroshi,JPX, Metal film forming method.
  14. Feustel, Frank; Werner, Thomas; Frohberg, Kai, Metallization system of a semiconductor device comprising extra-tapered transition vias.
  15. Luke Zhang ; Ruiping Wang ; Ida Ariani Adisaputro ; Kwang-Soo Kim, Method and apparatus for etch passivating and etching a substrate.
  16. DeOrnellas Stephen P. ; Cofer Alferd ; Rajora Paritosh, Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls.
  17. Stephen P. DeOrnellas ; Alferd Cofer ; Paritosh Rajora, Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls.
  18. Zhang Luke ; Wang Ruiping ; Adisaputro Ida Ariani ; Kim Kwang-Soo, Method and apparatus for etching a substrate with reduced microloading.
  19. Lee Shing-Long,TWX ; Huang Julie,TWX, Method for edge profile and design rules control.
  20. Chung Seong Woo,KRX, Method for etching contact.
  21. Mizukoshi Masataka,JPX ; Yamaguchi Ichiro,JPX ; Yoshikawa Masahiro,JPX ; Otake Koki,JPX ; Kasai Junichi,JPX, Method for fabricating bump forming plate member.
  22. Yang, Wenge; Subramanian, Ramkumar; Wang, Fei; Shen, Lewis, Method for forming SAC using a dielectric as a BARC and FICD enlarger.
  23. Fernando Gonzalez ; Gurtej S. Sandhu ; Mike P. Violette, Method for forming conductors in semiconductor devices.
  24. Gonzalez, Fernando; Sandhu, Gurtej S.; Violette, Mike P., Method for forming conductors in semiconductor devices.
  25. Gonzalez, Fernando; Sandhu, Gurtej S.; Violette, Mike P., Method for forming conductors in semiconductor devices.
  26. Gonzalez, Fernando; Sandhu, Gurtej S.; Violette, Mike P., Method for forming conductors in semiconductor devices.
  27. Gonzalez,Fernando; Sandhu,Gurtej S.; Violette,Mike P., Method for forming conductors in semiconductor devices.
  28. Wu Kuo-Chang,TWX, Method for forming tapered polysilicon plug and plug formed.
  29. Hwang Jeng H., Method for removing redeposited veils from etched platinum.
  30. Hwang Jeng H., Method for removing redeposited veils from etched platinum.
  31. Hwang Jeng H., Method for removing redeposited veils from etched platinum.
  32. Richter,Karola; Fischer,Daniel, Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate.
  33. Hwang, Jeng H.; Ying, Chentsau; Chiang, Kang-Lie; Mak, Steve S. Y., Method of etching an anisotropic profile in platinum.
  34. Fernando Gonzalez ; Gurtej S. Sandhu ; Mike P. Violette, Method of fabricating a memory device.
  35. Ra Kyeong Man,KRX, Method of fabricating flash memory with dissymmetrical floating gate.
  36. Kwak Noh Jung,KRX ; Kim Choon Hwan,KRX, Method of forming a contact hole of a semiconductor device.
  37. Shan Ende ; Lau Gorley ; Geha Sam G., Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit.
  38. Sardella John C. ; Kalnitsky Alexander ; Spinner ; III Charles R. ; Foulks ; Sr. Robert Carlton, Method of improving photoresist adhesion on a dielectric layer.
  39. Asai Shuji,JPX ; Oikawa Hirokazu,JPX, Method of manufacturing semiconductor device.
  40. Nakamura Yuji,JPX ; Sato Yoshinori,JPX ; Saita Yoshiaki,JPX, Method of manufacturing thermal head.
  41. Hwang, Jeng H., Method of plasma etching platinum.
  42. Scharnagl, Thomas; Staufer, Berthold, Method of producing bipolar transistor structures in a semiconductor process.
  43. Mehrad Freidoon ; Ambrose Thomas M. ; Tsung Lancy Y., Method to reduce source-line resistance in flash memory with sti.
  44. Clevenger,Lawrence A.; Dalton,Timothy Joseph; Hsu,Louis C.; Murray,Conal Eugene; Radens,Carl; Wong,Kwong Hon; Yang,Chih Chao, Modified via bottom structure for reliability enhancement.
  45. DeOrnellas Stephen P. ; Cofer Alferd ; Vail Robert C., Plasma etch reactor and method for emerging films.
  46. Stephen P. DeOrnellas ; Alferd Cofer ; Robert C. Vail, Plasma etch reactor and method for emerging films.
  47. Stephen P. DeOrnellas ; Leslie G. Jerde ; Alferd Cofer ; Robert C. Vail ; Kurt A. Olson, Plasma etch reactor having a plurality of magnets.
  48. Iriguchi, Chiharu, Semiconductor device and method of manufacturing semiconductor device.
  49. Taniguchi Toshio,JPX ; Nukui Kenji,JPX ; Burki Ibrahim ; Huang Richard ; Chan Simon ; Imaoka Kazunori,JPX ; Mochizuki Kazutoshi,JPX, Semiconductor device having interlayer insulator and method for fabricating thereof.
  50. Ra Kyeong Man,KRX, Semiconductor flash memory device and fabrication method of same.
  51. Akram Salman ; Lowrey Tyler A., Semiconductor processing method of forming an insulating dielectric layer and a contact opening therein.
  52. Wang Pei-Jan (Hsin-Chu TWX) Chou Kuei-Lung (Hsin-Chu TWX) Lin Jiunn-Jyi (Hsin-Chu TWX) Chang Hsien-Wen (Hsin-Chu TWX), Taper etching without re-entrance profile.
  53. Dutton, David T; Dean, Anthony B, Three dimensional etching process.
  54. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  55. Wang Fei ; Chen Susan, Use of hard masks during etching of openings in integrated circuits for high etch selectivity.
  56. Sakai Eishirou,JPX ; Yamagishi Kazuo,JPX ; Sakaguchi Haruki,JPX ; Tokuno Hideyuki,JPX, Vertical MOSFET having penetrating wiring layers.
  57. Lin Yung-Fa,TWX, Vertical via/contact.
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