초록 ▼

To reduce harmonics in an induction machine (33) which is fed by a self-commutated inverter (30), the trajectory of the flux vector of the induction machine is conducted along an edge path having at least 2pㆍqㆍm edges, where p is an integral number ≥1, q≥2 is the number of voltage stages of the inve

To reduce harmonics in an induction machine (33) which is fed by a self-commutated inverter (30), the trajectory of the flux vector of the induction machine is conducted along an edge path having at least 2pㆍqㆍm edges, where p is an integral number ≥1, q≥2 is the number of voltage stages of the inverter and m≥2 is the number of phases of the induction machine. In this arrangement, the flux vector is alternatingly conducted along straight and zig-zag segments. This reduction is essentially achieved by means of at least one second flux conducting circuit having a second coordinate con=verter (56) and a second comparator (57) in addition to a first flux conducting circuit having a first coordinate converter (54) and first comparator (46), the flux components (ybybybyb

대표청구항 ▼

Device for operating an induction machine (33) via a self-commutated inverter (30, Q1-Ql), (a) which exhibits a flux conducting circuit for controlling the inverter, (b) the flux conducting circuit exhibiting a first comparator (46, V1) for comparing m first actual flux value components (y1-y3; y11-

Device for operating an induction machine (33) via a self-commutated inverter (30, Q1-Ql), (a) which exhibits a flux conducting circuit for controlling the inverter, (b) the flux conducting circuit exhibiting a first comparator (46, V1) for comparing m first actual flux value components (y1-y3; y11-y1m) of the induction machine (33) with at least one nominal flux value (ys), m=the number of phases, (c) m first comparator output signals (K11-K13) produced by this comparison being supplied via a signal converter (36) to the inverter (30), wherein (d) the output of the first comparator (46, V1) is control-connected, on the one hand, via a phase shifter device (47, 98) to a selection circuit (48, 99) for a phase shift of 180°+180°/m and (e) on the other hand, via at least one logic circuit (Y, Y21-Yp-1) to this selection circuit, (f) the output of the selection circuit is effectively connected to the signal converter (36), (g) at least one second coordinate converter (56, KW1, KW2, KW2′) is provided which supplies m second actual flux value components (ybybybybybybyybybybybys), (h) m second comparator output signals (K11′-K1m′, K21′-K2m′) produced by this second comparator are supplied to the at least one logic circuit, (i) the logic circuit exhibits elements (63-73) for logically combining the first and second comparator output signals in accordance with the following relation: Z2=K11≠K11′ K12≠K12′ ...K1m≠K1m′, [Figure] for j=3 . . . p.