초록 ▼

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped juncti

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

대표청구항 ▼

An LDD transistor comprising a semiconductor substrate bearing thereon a gate insulating layer and a gate, characterized in that said gate includes a central portion and a pair of outboard portions straddling said central portion, each of said central and outboard portions having laterally spaced al

An LDD transistor comprising a semiconductor substrate bearing thereon a gate insulating layer and a gate, characterized in that said gate includes a central portion and a pair of outboard portions straddling said central portion, each of said central and outboard portions having laterally spaced alignment edges, first doped source and drain regions in said substrate have their facing ends in alignment with said aligment edges of said central portion, second doped source and drain regions in said substrate having their facing ends in alignment with said alignment edges of said outboard portions, said first doped source and drain regions being more lightly doped than said second doped source and drain regions, and said central portion and said outboard portions each include a conductive region, contiguous with said gate insulating layer, whereby said conductive regions extend from one of said outboard portion alignment edges to the other of said outboard portion alignment edges.