초록 ▼

A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical

A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more densely since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

대표청구항 ▼

An integrated circuit packaging structure comprising: an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface and a lower surface, and being formed having an array of conductive

An integrated circuit packaging structure comprising: an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface and a lower surface, and being formed having an array of conductive nodes protruding from said lower surface to provide electrical coupling to said internal circuits; a support substrate having an upper surface and a lower surface, said substrate having a plurality of through vias formed therein and extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to said array of conductive nodes on said lower surface of said integrated circuit element; said substrate further comprising conductor means within said through vias and extending from said substrate upper surface to said substrate lower surface; an electrical interconnect layer comprising a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface, said interconnect layer further having a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to said array of conductive nodes on said integrated circuit element and being adapted for coupling to said interconnect elements within said interconnect layer; and wherein said lower surface of said integrated circuit element is formed adjacent to said upper surface of said substrate so as to align said conductive nodes with said through vias and to electrically couple said conductive nodes with said conductor means; said upper surface of said interconnect layer is formed adjacent to said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.