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A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single wr

A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations. By writing data into the input registers instead of the register file memory in a previous cycle, the time required for writing is reduced to a minimum.

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A dual port read/write memory having a single write input sort comprising: a random access memory (RAM) array having a plurality of addressable storage locations, said RAM having said single write port including a set of write data, address and write enable input terminals; clocked input register me

A dual port read/write memory having a single write input sort comprising: a random access memory (RAM) array having a plurality of addressable storage locations, said RAM having said single write port including a set of write data, address and write enable input terminals; clocked input register means for storing sets of write data, address and command information associated with a pair of ports; multiplexer selector means connected to said register means for receiving said sets of information and said multiplexer selector means being connected to apply said sets of information to corresponding ones of said write data, address and write enable terminals of said RAM; and, input means for applying a sequence of timing signals to said memory during each cycle of operation including a bistate write select signal applied to said multiplexer selector means and first and second sequential write pulse signals applied to said RAM write enable input terminal, said RAM being enabled by said first write pulse signal to write said data of one of said ports into one of said plurality of locations specified by said address associated therewith in response to said command information applied by said selector means when said write select signal is in a first state and said RAM being enabled by said second write pulse signal to write said data of another one of said ports into another one of said locations specified by said address associated therewith in response to said command information when said write select signal is in a second state so as to provide a dual port write capability for said each cycle of operation.