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[미국특허] Electronic package with integrated distributed decoupling capacitors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0300681 (1989-01-19)
발명자 / 주소
  • Brown Michael B. (Binghamton NY) Ebert William S. (Endicott NY) Olson Leonard T. (Endwell NY) Sloma Richard R. (Endicott NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 41  인용 특허 : 22

초록 ▼

A semiconductor chip carrier includes a plurality of distributed high frequency decoupling capacitors as an integral part of the carrier. The distributed capacitors are formed as a part of the first and second layers of metallurgy and separated by a layer of thin film dielectric material built up on

대표청구항 ▼

An electronic packaging structure comprising: (a) a substrate; (b) a layer of metallurgy on the substrate, said layer of metallurgy having a pad for unitary intermetallic electrical connections and including at least one portion forming a first plate of a capacitor; (c) a dielectric layer covering t

이 특허에 인용된 특허 (22) 인용/피인용 타임라인 분석

  1. Bajorek Christopher H. (Goldens Bridge NY) Chance Dudley A. (Danbury CT) Ho Chung W. (Chappaqua NY), Capacitive chip carrier and multilayer ceramic capacitors.
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  2. Thompson David A. (South Salem NY), Chip package with high capacitance, stacked vlsi/power sheets extending through slots in substrate.
    상세보기
  3. Jordan Lester J. (Smethport PA) Platko Steve (Bradford PA), Electrical device assembly and method.
    상세보기
  4. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Electronic package assembly method.
    상세보기
  5. Ikeno Hitoshi (Tokyo JPX), Hermetically sealed package.
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  6. Ecker Mario E. (Poughkeepsie NY) Olson Leonard T. (Jericho VT), High density interconnection means for chip carriers.
    상세보기
  7. Scandurra, Aldo M., High isolation multicoupling apparatus.
    상세보기
  8. Doo Ven Y. (Poughkeepsie NY), High performance integrated circuit semiconductor package and method of making.
    상세보기
  9. Fraser ; Jr. Donald L. (Warren Township ; Somerset County NJ) Tompsett Michael F. (New Providence NJ), High-ratio-accuracy capacitor geometries for integrated circuits.
    상세보기
  10. Leary Burton (Hingham MA) Silverio Shaun (Beverly MA), High-speed wire wrap board.
    상세보기
  11. Miyauchi Akira (Kawasaki JPX) Nishimoto Hiroshi (Tokyo JPX) Okiyama Tadashi (Kawasaki JPX) Kitasagami Hiroo (Kawasaki JPX) Sugimoto Masahiro (Yokosuka JPX) Tamada Haruo (Yokohama JPX) Emori Shinji (U, Integrated circuit device having stacked conductive layers connecting circuit elements therethrough.
    상세보기
  12. Ciccio Joseph A. (Winchester MA) Thun Rudolf E. (Carlisle MA) Fardy Harry J. (Chelmsford MA), Integrated circuit device package interconnect means.
    상세보기
  13. Durney David J. (Holland PA) Lockhart ; Jr. James A. (Basking Ridge NJ), Integrated circuit module with integral capacitor.
    상세보기
  14. Ecker Mario E. (Poughkeepsie NY) Olson Leonard T. (Jericho VT), Integrated circuit package.
    상세보기
  15. Chance Dudley A. (Danbury CT) Kopcsay Gerard V. (Yorktown Heights NY), LSI Chip carrier with buried repairable capacitor with low inductance leads.
    상세보기
  16. Chance Dudley A. (Danbury CT) Ho Chung W. (Chappaqua NY) Reiley Timothy C. (Ridgefield CT), Low inductance MLC capacitor with metal impregnation and solder bar contact.
    상세보기
  17. Jaffe Richard A. (24115 Bessemer St. Woodland Hills CA 91367), Micromodular electronic package.
    상세보기
  18. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Multi-layer flexible film module.
    상세보기
  19. Bajorek Christopher H. (Goldens Bridge NY) Chance Dudley A. (Danbury CT) Ho Chung W. (Chappaqua NY) Thompson David A. (South Salem NY), Multiple layer, ceramic carrier for high switching speed VLSI chips.
    상세보기
  20. Ecker, Mario E.; Olson, Leonard T., Repairable multi-level overlay system for semiconductor device.
    상세보기
  21. Feinberg Irving (Poughkeepsie NY) Wu Leon L. (Hopewell Junction NY), Thick film capacitor having very low internal inductance.
    상세보기
  22. Nagashima Toshio (Yokohama JPX) Saitoh Takeshi (Yokohama JPX) Hatashita Hiroshi (Tokyo JPX) Shinagawa Mitsuhisa (Fujisawa JPX), Thick film multilayer substrate.
    상세보기

이 특허를 인용한 특허 (41) 인용/피인용 타임라인 분석

  1. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
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  2. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
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  3. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
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  4. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.
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  5. Bloom Terry R. ; Cooper Richard O. ; Reinhard Robert L., Ball grid array R-C network with high density.
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  6. Bloom Terry R. ; Cooper Richard O. ; Reinhard Robert L., Ball grid array capacitor.
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  7. Bloom,Terry R., Ball grid array package.
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  8. Poole, David; Bloom, Terry R.; Cooper, Richard, Ball grid array package having testing capability after mounting.
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  9. Bloom Terry R. ; Burry Stephen W. ; Seffernick Lewis L. ; VandenBoom Robert M. ; Zdanys ; Jr. John, Ball grid array resistor network.
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  10. Poole David L. ; Reinhard Robert L. ; Cooper Richard O. ; DeMars Richard S., Ball grid array resistor terminator network.
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  11. Giri Ajay P. ; Kamath Sundar M. ; O'Connor Daniel P. ; Patel Rajesh B. ; Stoller Herbert I. ; Studzinski Lisa M. ; Walling Paul R., Direct deposit thin film single/multi chip module.
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  12. Giri Ajay P. ; Kamath Sundar M. ; O'Connor Daniel P. ; Patel Rajesh B. ; Stoller Herbert I. ; Studzinski Lisa M. ; Walling Paul R., Direct deposit thin film single/multi chip module.
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  13. Geissinger,John D.; Harvey,Paul M.; Kieschke,Robert R., Electronic package with integrated capacitor.
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  14. Geissinger,John D.; Harvey,Paul M.; Kieschke,Robert R., Electronic package with integrated capacitor.
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  15. Lewis Robert L. (Apalachin NY) Sebesta Robert D. (Endicott NY) Waits Daniel M. (Vestal NY), Electronic package with multilevel connections.
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  16. Anthony, Anthony A.; Anthony, William M., Energy conditioning circuit arrangement for integrated circuit.
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  17. Song,Eun Seok; Lee,Hee Seok, Integrated circuit chip package having a ring-shaped silicon decoupling capacitor.
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  18. Parker Robert H. (Oakton VA) Pommer Richard J. (Canyon CA), Integrated circuit component package with integral passive component.
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  19. Christensen Todd Alan ; Sheet ; II John Edward, Integrated circuit having integral decoupling capacitor.
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  20. Christensen Todd Alan ; Sheets ; II John Edward, Integrated circuit having integral decoupling capacitor.
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  21. Bertin Claude Louis ; Howell Wayne John ; Tonti William Robert Patrick ; Zalesnski Jerzy Maria, Integrated high-performance decoupling capacitor.
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  22. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.
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  23. Bloom Terry R. ; Cooper Richard O. ; Poole David L., Low cross talk ball grid array resistor network.
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  24. Fung Laurie P., Low inductance decoupling capacitor arrangement.
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  25. Antu,Rafael; Drews,Cathy Marie; Plomgren,David A.; Takken,Todd Edward, Method and apparatus for providing improved loop inductance of decoupling capacitors.
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  26. Anthony, William M.; Anthony, David; Anthony, Anthony, Method for making internally overlapped conditioners.
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  27. Kweon Young Do,KRX ; Kim Jung Jin,KRX ; Song Young Jae,KRX ; Song Young Hee,KRX ; Lee Joung Rhang,KRX, Packing structure of semiconductor packages.
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  28. Ninomiya, Ryoji, Printed circuit board and electronic equipment using the board.
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  29. Ryoji Ninomiya JP, Printed circuit board and electronic equipment using the board.
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  30. Karlsson, Ulf G., Printed circuit board with embedded circuit component.
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  31. Higgins ; Jr. Robert J. (Sunrise FL), Radio frequency filter feedthrough structure for multilayer circuit boards.
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  32. Ginn Steven N. ; Hufford James N. ; Zdanys ; Jr. John ; Burry Stephen W. ; Seffernick Lewis L. ; VandenBoom Robert M., Resistor network with solder sphere connector.
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  33. Farooq Mukta Shaji ; Jackson Raymond Alan ; Ray Sudipta Kumar, Reworkability method for wirebond chips using high performance capacitor.
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  34. Farooq Mukta Shaji ; Jackson Raymond Alan ; Ray Sudipta Kumar, Reworkability solution for wirebound chips using high performance capacitor.
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  35. Seshan, Krishna, Selectable decoupling capacitors for integrated circuit and methods of use.
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  36. Seshan,Krishna, Selectable decoupling capacitors for integrated circuits and associated methods.
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  37. Ouchida Takayuki,JPX, Semiconductor device.
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  38. Nakano,Takashi; Tohya,Hirokazu, Semiconductor device, semiconductor circuit and method for producing semiconductor device.
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  39. Endo,Mitsuyoshi; Matsuo,Mie; Takubo,Chiaki, Semiconductor device, semiconductor package member, and semiconductor device manufacturing method.
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  40. Das, Rabindra N.; Egitto, Frank D.; Lauffer, John M.; Lin, How T., Substrate having internal capacitor and method of making same.
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  41. Fletcher,Richard; Gershenfeld,Neil, Tuneable wireless tags using spatially inhomogeneous structures.
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